-----Original Message-----
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Don=

gsheng

Wang
Sent: Tuesday, September 24, 2013 2:59 PM
To: Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
Subject: [PATCH v4 4/4] powerpc/85xx: add sysfs for pw20 state and altive=

c idle

=20
From: Wang Dongsheng <redacted>
=20
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
=20
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
=20
Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~47(ns): TB[63]
48~95(ns): TB[62]
96~191(ns): TB[61]
192~383(ns): TB[62]
384~767(ns): TB[60]
...
=20
Signed-off-by: Wang Dongsheng <redacted>
---
*v4:
Move code from 85xx/common.c to kernel/sysfs.c.
=20
Remove has_pw20_altivec_idle function.
=20
Change wait "entry_bit" to wait time.
=20
 arch/powerpc/kernel/sysfs.c | 291 ++++++++++++++++++++++++++++++++++++++=

++++++

);

=20
 #endif /* CONFIG_PPC64 */
=20
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT		63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+	u64 cycle;
+
+	cycle =3D div_u64(ns, 1000 / tb_ticks_per_usec);

When tb_ticks_per_usec  > 1000 (timebase frequency > 1GHz) then this will a=
lways be ns, which is not correct, no?=20

+	if (!cycle)
+		return 0;
+
+	return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+	u32 *value =3D val;
+
+	*value =3D mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+	value &=3D PWRMGTCR0_PW20_WAIT;
+
+	return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+	u32 *value =3D val;
+	u32 pw20_state;
+
+	pw20_state =3D mfspr(SPRN_PWRMGTCR0);
+
+	if (*value)
+		pw20_state |=3D PWRMGTCR0_PW20_WAIT;
+	else
+		pw20_state &=3D ~PWRMGTCR0_PW20_WAIT;
+
+	mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	if (value > 1)
+		return -EINVAL;
+
+	smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
+
+	return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	u32 value;
+	u64 tb_cycle;
+	u64 time;
+
+	unsigned int cpu =3D dev->id;
+
+	if (!pw20_wt) {
+		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+		value =3D (value & PWRMGTCR0_PW20_ENT) >>
+					PWRMGTCR0_PW20_ENT_SHIFT;
+
+		tb_cycle =3D (1 << (MAX_BIT - value)) * 2;
+		time =3D tb_cycle * (1000 / tb_ticks_per_usec) - 1;

Similar to above comment.

-Bharat

+	} else {
+		time =3D pw20_wt;
+	}
+
+	return sprintf(buf, "%llu\n", time);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+	u32 *value =3D val;
+	u32 pw20_idle;
+
+	pw20_idle =3D mfspr(SPRN_PWRMGTCR0);
+
+	/* Set Automatic PW20 Core Idle Count */
+	/* clear count */
+	pw20_idle &=3D ~PWRMGTCR0_PW20_ENT;
+
+	/* set count */
+	pw20_idle |=3D ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
+
+	mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	u32 entry_bit;
+	u64 value;
+
+	unsigned int cpu =3D dev->id;
+
+	if (kstrtou64(buf, 0, &value))
+		return -EINVAL;
+
+	if (!value)
+		return -EINVAL;
+
+	entry_bit =3D get_idle_ticks_bit(value);
+	if (entry_bit > MAX_BIT)
+		return -EINVAL;
+
+	pw20_wt =3D value;
+	smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+				&entry_bit, 1);
+
+	return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+	value &=3D PWRMGTCR0_AV_IDLE_PD_EN;
+
+	return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_altivec_idle(void *val)
+{
+	u32 *value =3D val;
+	u32 altivec_idle;
+
+	altivec_idle =3D mfspr(SPRN_PWRMGTCR0);
+
+	if (*value)
+		altivec_idle |=3D PWRMGTCR0_AV_IDLE_PD_EN;
+	else
+		altivec_idle &=3D ~PWRMGTCR0_AV_IDLE_PD_EN;
+
+	mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	if (value > 1)
+		return -EINVAL;
+
+	smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
+
+	return count;
+}
+
+static ssize_t show_altivec_idle_wait_time(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	u32 value;
+	u64 tb_cycle;
+	u64 time;
+
+	unsigned int cpu =3D dev->id;
+
+	if (!altivec_idle_wt) {
+		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+		value =3D (value & PWRMGTCR0_AV_IDLE_CNT) >>
+					PWRMGTCR0_AV_IDLE_CNT_SHIFT;
+
+		tb_cycle =3D (1 << (MAX_BIT - value)) * 2;
+		time =3D tb_cycle * (1000 / tb_ticks_per_usec) - 1;
+	} else {
+		time =3D altivec_idle_wt;
+	}
+
+	return sprintf(buf, "%llu\n", time);
+}
+
+static void set_altivec_idle_wait_entry_bit(void *val)
+{
+	u32 *value =3D val;
+	u32 altivec_idle;
+
+	altivec_idle =3D mfspr(SPRN_PWRMGTCR0);
+
+	/* Set Automatic AltiVec Idle Count */
+	/* clear count */
+	altivec_idle &=3D ~PWRMGTCR0_AV_IDLE_CNT;
+
+	/* set count */
+	altivec_idle |=3D ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
+
+	mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle_wait_time(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	u32 entry_bit;
+	u64 value;
+
+	unsigned int cpu =3D dev->id;
+
+	if (kstrtou64(buf, 0, &value))
+		return -EINVAL;
+
+	if (!value)
+		return -EINVAL;
+
+	entry_bit =3D get_idle_ticks_bit(value);
+	if (entry_bit > MAX_BIT)
+		return -EINVAL;
+
+	altivec_idle_wt =3D value;
+	smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
+				&entry_bit, 1);
+
+	return count;
+}
+
+/*
+ * Enable/Disable interface:
+ * 0, disable. 1, enable.
+ */
+static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
+static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_=

idle);