[PATCH] powerpc: net: filter: fix DIVWU instruction opcode

Currently DIVWU stands for *signed* divw opcode:

7d 2a 4b 96 	divwu   r9,r10,r9
7d 2a 4b d6 	divw    r9,r10,r9

Use the *unsigned* divw opcode for DIVWU.

Signed-off-by: Vladimir Murzin <redacted>
---
 arch/powerpc/include/asm/ppc-opcode.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index d7fe9f5..c91842c 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h

@@ -218,7 +218,7 @@
 #define PPC_INST_MULLW			0x7c0001d6
 #define PPC_INST_MULHWU			0x7c000016
 #define PPC_INST_MULLI			0x1c000000
-#define PPC_INST_DIVWU			0x7c0003d6
+#define PPC_INST_DIVWU			0x7c000396
 #define PPC_INST_RLWINM			0x54000000
 #define PPC_INST_RLDICR			0x78000004
 #define PPC_INST_SLW			0x7c000030

-- 
1.7.10.4

Vladimir Murzin [off-list ref] wrote:

Currently DIVWU stands for *signed* divw opcode:

7d 2a 4b 96 	divwu   r9,r10,r9
7d 2a 4b d6 	divw    r9,r10,r9

Use the *unsigned* divw opcode for DIVWU.

This looks like it's in only used in the BPF JIT code.  

Matt, any chance you an ACK/NACK this?

Mikey

On 12 Sep 2013, at 10:02, Michael Neuling [off-list ref] wrote:

Vladimir Murzin [off-list ref] wrote:
=20

quoted

Currently DIVWU stands for *signed* divw opcode:
=20
7d 2a 4b 96    divwu   r9,r10,r9
7d 2a 4b d6    divw    r9,r10,r9
=20
Use the *unsigned* divw opcode for DIVWU.

=20
This looks like it's in only used in the BPF JIT code. =20
=20
Matt, any chance you an ACK/NACK this?

Sure, that looks sensible, thanks Vladimir.=20

Acked-by: Matt Evans <redacted>

=20
Mikey
=20

quoted

=20
Signed-off-by: Vladimir Murzin <redacted>
---
arch/powerpc/include/asm/ppc-opcode.h |    2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
=20

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include=

/asm/ppc-opcode.h

quoted

index d7fe9f5..c91842c 100644

--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h

@@ -218,7 +218,7 @@

#define PPC_INST_MULLW            0x7c0001d6
#define PPC_INST_MULHWU            0x7c000016
#define PPC_INST_MULLI            0x1c000000
-#define PPC_INST_DIVWU            0x7c0003d6
+#define PPC_INST_DIVWU            0x7c000396
#define PPC_INST_RLWINM            0x54000000
#define PPC_INST_RLDICR            0x78000004
#define PPC_INST_SLW            0x7c000030
--=20
1.7.10.4
=20

On Thu, Sep 12, 2013 at 10:28:03AM +0930, Matt Evans wrote:

On 12 Sep 2013, at 10:02, Michael Neuling [off-list ref] wrote:

quoted

Vladimir Murzin [off-list ref] wrote:

quoted

Currently DIVWU stands for *signed* divw opcode:

7d 2a 4b 96    divwu   r9,r10,r9
7d 2a 4b d6    divw    r9,r10,r9

Use the *unsigned* divw opcode for DIVWU.

This looks like it's in only used in the BPF JIT code.  

Matt, any chance you an ACK/NACK this?

Sure, that looks sensible, thanks Vladimir. 

Acked-by: Matt Evans <redacted>

Thanks!

Vladimir

quoted

Mikey

quoted

Signed-off-by: Vladimir Murzin <redacted>
---
arch/powerpc/include/asm/ppc-opcode.h |    2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index d7fe9f5..c91842c 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h

@@ -218,7 +218,7 @@

#define PPC_INST_MULLW            0x7c0001d6
#define PPC_INST_MULHWU            0x7c000016
#define PPC_INST_MULLI            0x1c000000
-#define PPC_INST_DIVWU            0x7c0003d6
+#define PPC_INST_DIVWU            0x7c000396
#define PPC_INST_RLWINM            0x54000000
#define PPC_INST_RLDICR            0x78000004
#define PPC_INST_SLW            0x7c000030
-- 
1.7.10.4