On Tue, 2013-08-06 at 18:23 +0800, Kevin Hao wrote:
We don't need to flush the dcache and invalidate the icache on the
CPU which has CPU_FTR_COHERENT_ICACHE set.
Actually we probably need an isync...
Ben.
quoted hunk ↗ jump to hunk
Signed-off-by: Kevin Hao <redacted>
---
arch/powerpc/kernel/misc_64.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index a781566..32e78e2 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -207,6 +207,9 @@ _GLOBAL(flush_inval_dcache_range)
* void __flush_dcache_icache(void *page)
*/
_GLOBAL(__flush_dcache_icache)
+BEGIN_FTR_SECTION
+ blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
/*
* Flush the data cache to memory
*