quoted

 	clockgen: global-utilities@e1000 {
-		compatible =3D "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
+		compatible =3D "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0",
+				   "fixed-clock";
+		clock-output-names =3D "sysclk";
+		#clock-cells =3D <0>;

=20
Does U-Boot fill in clock-frequency here?
=20

Yes, clock-frequency will be filled by uboot.
You suggested we'd better not add it here.

quoted

+		#address-cells =3D <1>;
+		#size-cells =3D <0>;
+		pll0: pll0@800 {
+			#clock-cells =3D <1>;
+			reg =3D <0x800>;
+			compatible =3D "fsl,core-pll-clock";
+			clocks =3D <&clockgen>;
+			clock-output-names =3D "pll0", "pll0-div2", "pll0-div4";
+		};
+		pll1: pll1@820 {
+			#clock-cells =3D <1>;
+			reg =3D <0x820>;
+			compatible =3D "fsl,core-pll-clock";
+			clocks =3D <&clockgen>;
+			clock-output-names =3D "pll1", "pll1-div2", "pll1-div4";
+		};

=20
Please leave a blank line between properties and nodes, and between nodes=

.

=20

OK, will add.

What does reg represent?  Where is the binding for this?
=20
The compatible is too vague.

Reg is register offset. I should have had a binding document.
About the compatible, you should pointed it out earlier in SDK review.
It is too later to change since the clock driver is merged for months altho=
ugh=20
I sent this patch first.
Besides, it is not too bad because other arch use the similar name.

Regards,
Yuantian

=20

quoted

+		mux0: mux0@0 {
+			#clock-cells =3D <0>;
+			reg =3D <0x0>;
+			compatible =3D "fsl,core-mux-clock";
+			clocks =3D <&pll0 0>, <&pll0 1>, <&pll0 2>,
+				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
+			clock-names =3D "pll0_0", "pll0_1", "pll0_2",
+				"pll1_0", "pll1_1", "pll1_2";
+			clock-output-names =3D "cmux0";
+		};

=20
What does reg represent?  Where is the binding for this?
=20
The compatible is too vague.
=20
-Scott