Re: [PATCH] powerpc/pci: fix PCI-e check link issue
From: Rojhalat Ibrahim <hidden>
Date: 2013-05-21 12:08:07
On Friday 17 May 2013 15:35:29 Yuanquan Chen wrote:
For Freescale powerpc platform, the PCI-e bus number uses the reassign mode by default. It means the second PCI-e controller's hose->first_busno is the first controller's last bus number adding 1. For some hotpluged device(or controlled by FPGA), the device is linked to PCI-e slot at linux runtime. It needs rescan for the system to add it and driver it to work. It successes to rescan the device linked to the first PCI-e controller's slot, but fails to rescan the device linked to the second PCI-e controller's slot. The cause is that the bus->number is reset to 0, which isn't equal to the hose->first_busno for the second controller checking PCI-e link. So it doesn't really check the PCI-e link status, the link status is always no_link. The device won't be really rescaned. Reset the bus->number to hose->first_busno in the function fsl_pcie_check_link(), it will do the real checking PCI-e link status for the second controller, the device will be rescaned. Signed-off-by: Yuanquan Chen <redacted>
Tested-by: Rojhalat Ibrahim <redacted>
quoted hunk ↗ jump to hunk
--- arch/powerpc/sysdev/fsl_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 028ac1f..534597a 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c@@ -64,7 +64,7 @@ static int fsl_pcie_check_link(struct pci_controller*hose) if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { if (hose->ops->read == fsl_indirect_read_config) { struct pci_bus bus; - bus.number = 0; + bus.number = hose->first_busno; bus.sysdata = hose; bus.ops = hose->ops; indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);