[PATCH v2 13/15] powerpc/85xx: add support for e6500 L1 cache operation
From: Zhao Chenhui <hidden>
Date: 2013-04-19 10:49:47
Also in:
lkml
Subsystem:
linux for powerpc (32-bit and 64-bit), the rest · Maintainers:
Madhavan Srinivasan, Michael Ellerman, Linus Torvalds
From: Chen-Hui Zhao <redacted> The L1 Data Cache of e6500 contains no modified data, no flush is required. Signed-off-by: Zhao Chenhui <redacted> Signed-off-by: Li Yang <redacted> Signed-off-by: Andy Fleming <redacted> --- arch/powerpc/kernel/fsl_booke_cache.S | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/fsl_booke_cache.S b/arch/powerpc/kernel/fsl_booke_cache.S
index 232c47b..24a52bb 100644
--- a/arch/powerpc/kernel/fsl_booke_cache.S
+++ b/arch/powerpc/kernel/fsl_booke_cache.S@@ -65,13 +65,22 @@ _GLOBAL(flush_dcache_L1) blr +#define PVR_E6500 0x8040 + /* Flush L1 d-cache, invalidate and disable d-cache and i-cache */ _GLOBAL(__flush_disable_L1) +/* L1 Data Cache of e6500 contains no modified data, no flush is required */ + mfspr r3, SPRN_PVR + rlwinm r4, r3, 16, 0xffff + lis r5, 0 + ori r5, r5, PVR_E6500@l + cmpw r4, r5 + beq 2f mflr r10 bl flush_dcache_L1 /* Flush L1 d-cache */ mtlr r10 - msync +2: msync mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */ li r5, 2 rlwimi r4, r5, 0, 3
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1.7.3