Michael Neuling [off-list ref] wrote:

quoted

commit 279c0615917b959a652e81f4ad0d886e2d426d85
Author: Jimi Xenidis [off-list ref]
Date:   Wed Dec 5 13:43:22 2012 -0500

    powerpc/book3e: IBM Blue Gene/Q Quad Processing eXtention (QPX)
    
    This enables kernel support for the QPX extention and is intended for
    processors that support it, usually an IBM Blue Gene processor.
    Turning it on does not effect other processors but it does add code
    and will quadruple the per thread save and restore area for the FPU
    (hense the name).  If you have enabled VSX it will only double the
    space.
    
    Signed-off-by: Jimi Xenidis [off-list ref]

Can you give a diagram of how the QPX registers are layed out.

+#if defined(CONFIG_PPC_QPX)
+#define TS_FPRWIDTH 4
+#elif defined(CONFIG_VSX)

Are they 256 bits wide?


+#define QVLFDXA(QRT,RA,RB)	\
+	.long (0x7c00048f | ((QRT) << 21) | ((RA) << 16) | ((RB) << 11))

Put this in ppc-opcode.h.

+#if defined(CONFIG_VSX) || defined(CONFIG_PPC_QPX)
+	/* they are the same MSR bit */

OMG!


+BEGIN_FTR_SECTION							\
+	SAVE_32VSRS(n,c,base);						\
+END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
+BEGIN_FTR_SECTION							\
+	SAVE_32QRS(n,c,base);						\
+END_FTR_SECTION_IFSET(CPU_FTR_QPX);	

I don't think we want to do this.  We are going to end up with 64
NOPS here somewhere.

I'd like to see this patch broken into different parts.

Also, have you boot tested this change on a VSX enabled box?

Also, this is going to clash with the transactional memory patches.

Mikey