Re: [PATCH] powerpc/perf: Add missing L2 constraint handling in Power7 PMU
From: Paul Mackerras <hidden>
Date: 2012-10-31 04:18:34
On Wed, Oct 31, 2012 at 01:09:56PM +1100, Michael Ellerman wrote:
If we have two cache events that require different settings of the L2SEL bits in MMCR1 then we can not schedule those events simultaneously. Add logic to the constraint handling to express that. Signed-off-by: Michael Ellerman <redacted>
Acked-by: Paul Mackerras <redacted>