Re: [RFC][PATCH 2/3] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver.

From
Kumar Gala <hidden>
Date
2012-09-19 13:52:35
Also in
linux-iommu, lkml
Reply to
unknown sender, 2012-09-19
On Sep 19, 2012, at 8:17 AM, [off-list ref] =
[off-list ref] wrote:
quoted hunk ↗ jump to hunk
From: Varun Sethi <redacted>
=20
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute, which allows setting of the
  LIODN specific stash id parameter through IOMMU API.
3. Added an attribute for enabling/disabling DMA to a particular
  memory window.
=20
Signed-off-by: Varun Sethi <redacted>
---
include/linux/iommu.h |   30 ++++++++++++++++++++++++++++++
1 files changed, 30 insertions(+), 0 deletions(-)
=20
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 7e83370..eaa40c6 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -44,6 +44,28 @@ struct iommu_domain_geometry {
	dma_addr_t aperture_start; /* First address that can be mapped   =
 */
	dma_addr_t aperture_end;   /* Last address that can be mapped    =
 */
	bool force_aperture;       /* DMA only allowed in mappable =
range? */
+
+	/* The subwindows field indicates number of DMA subwindows =
supported
quoted hunk ↗ jump to hunk
+	 * by the geometry. Following is the interpretation of
+	 * values for this field:
+	 * 0 : This implies that the supported geometry size is 1 MB
+         * with each subwindow size being 4KB. Thus number of =
subwindows
quoted hunk ↗ jump to hunk
+	 * being =3D 1MB/4KB =3D 256.
+	 * 1 : Only one DMA window i.e. no subwindows.
+	 * value other than 0 or 1 would indicate actual number of =
subwindows.
quoted hunk ↗ jump to hunk
+	 */
+	u32 subwindows;
+};
+
+/* This attribute corresponds to IOMMUs capable of generating
+ * a stash transaction. A stash transaction is typically a
+ * hardware initiated prefetch of data from memory to cache.
+ * This attribute allows configuring stashig specific parameters
+ * in the IOMMU hardware.
+ */
+struct iommu_stash_attribute {
+	u32 	cpu;	/* cpu number */
+	u32 	cache;	/* cache to stash to: L1,L2,L3 */
seems like this should be enum instead of u32 for cache

With enum being something like:

enum iommu_attr_stash_cache {
	IOMMU_ATTR_CACHE_L1,
	IOMMU_ATTR_CACHE_L2,
	IOMMU_ATTR_CACHE_L3,
};
quoted hunk ↗ jump to hunk
};
=20
struct iommu_domain {
@@ -60,6 +82,14 @@ struct iommu_domain {
enum iommu_attr {
	DOMAIN_ATTR_MAX,
	DOMAIN_ATTR_GEOMETRY,
+	/* Set the IOMMU hardware stashing
+	 * parameters.
+	 */
+	DOMAIN_ATTR_STASH,
+	/* Explicity enable/disable DMA for a
+         * particular memory window.
+         */
+	DOMAIN_ATTR_ENABLE,
};
=20
#ifdef CONFIG_IOMMU_API
--=20
1.7.4.1
=20
=20
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Thread (9 messages) 9 messages, 2 authors, last reply 2012-10-04
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