On Aug 7, 2012, at 11:06 PM, Varun Sethi wrote:
All SOC device error interrupts are muxed and delivered to the core
as a single MPIC error interrupt. Currently all the device drivers
requiring access to device errors have to register for the MPIC error
interrupt as a shared interrupt.
=20
With this patch we add interrupt demuxing capability in the mpic =
driver,
allowing device drivers to register for their individual error =
interrupts.
This is achieved by handling error interrupts in a cascaded fashion.
=20
MPIC error interrupt is handled by the "error_int_handler", which
subsequently demuxes it using the EISR and delivers it to the =
respective
drivers.=20
=20
The error interrupt capability is dependent on the MPIC EIMR register,
which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error
interrupt demuxing capability is dependent on the MPIC version and can
be used for versions >=3D 4.1.
=20
Signed-off-by: Varun Sethi <redacted>
Signed-off-by: Bogdan Hamciuc <redacted>
[In the initial version of the patch we were using handle_simple_irq
as the handler for cascaded error interrupts, this resulted
in issues in case of threaded isrs (with RT kernel). This issue was
debugged by Bogdan and decision was taken to use the handle_level_irq
handler]
---
arch/powerpc/include/asm/mpic.h | 14 ++++
arch/powerpc/sysdev/Makefile | 2 +-
arch/powerpc/sysdev/fsl_mpic_err.c | 149 =
++++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/mpic.c | 44 ++++++++++-
arch/powerpc/sysdev/mpic.h | 22 +++++
5 files changed, 229 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_mpic_err.c
applied to next
- k