Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the driver waits 32 IDLE patterns before returning the received data to the upper level. It means for instance about 1 second at 300 bauds.
This fix limits to one byte the waiting period.
Signed-off-by: Christophe Leroy <redacted>
@@ -872,7 +873,7 @@/* Using idle character time requires some additional tuning. */out_be16(&up->smc_mrblr,pinfo->rx_fifosize);-out_be16(&up->smc_maxidl,pinfo->rx_fifosize);+out_be16(&up->smc_maxidl,1);out_be16(&up->smc_brklen,0);out_be16(&up->smc_brkec,0);out_be16(&up->smc_brkcr,1);
On Tue, 14 Aug 2012 16:26:28 +0200
Christophe Leroy [off-list ref] wrote:
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the driver waits 32 IDLE patterns before returning the received data to the upper level. It means for instance about 1 second at 300 bauds.
This fix limits to one byte the waiting period.
Take a look how the 8250 does it - I think you want to set the value
based upon the data rate. Your patch will break it for everyone doing
high seed I/O.
Alan
On Tue, 14 Aug 2012 16:26:28 +0200
Christophe Leroy [off-list ref] wrote:
quoted
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the driver waits 32 IDLE patterns before returning the received data to the upper level. It means for instance about 1 second at 300 bauds.
This fix limits to one byte the waiting period.
Take a look how the 8250 does it - I think you want to set the value
based upon the data rate. Your patch will break it for everyone doing
high seed I/O.
Alan
I'm not sure I understand what you mean. As far as I can see 8250/16550
is working a bit different, as it is based on a fifo and triggers an
interrupt as soon as a given number of bytes is received. I also see
that in case this amount is not reached, there is a receive-timeout
which goes on after no byte is received for a duration of more than 4 bytes.
The PowerPC CPM is working differently. It doesn't use a fifo but
buffers. Buffers are handed to the microprocessor only when they are
full or after a timeout period which is adjustable. In the driver, the
buffers are configured with a size of 32 bytes. And the timeout is set
to the size of the buffer. That is this timeout that I'm reducing to 1
byte in my proposed patch. I can't see what it would break for high
speed I/O.
Christophe
The PowerPC CPM is working differently. It doesn't use a fifo but
buffers. Buffers are handed to the microprocessor only when they are
full or after a timeout period which is adjustable. In the driver, the
Which is different how - remembering we empty the FIFO on an IRQ
buffers are configured with a size of 32 bytes. And the timeout is set
to the size of the buffer. That is this timeout that I'm reducing to 1
byte in my proposed patch. I can't see what it would break for high
speed I/O.
How can a timeout be measured in "bytes". Can we have a bit more clarity
on how the hardware works and take it from there ?
Alan
The PowerPC CPM is working differently. It doesn't use a fifo but
buffers. Buffers are handed to the microprocessor only when they are
full or after a timeout period which is adjustable. In the driver, the
Which is different how - remembering we empty the FIFO on an IRQ
quoted
buffers are configured with a size of 32 bytes. And the timeout is set
to the size of the buffer. That is this timeout that I'm reducing to 1
byte in my proposed patch. I can't see what it would break for high
speed I/O.
How can a timeout be measured in "bytes". Can we have a bit more clarity
on how the hardware works and take it from there ?
Alan
The reference manual of MPC885 says the following about the MAX_IDL
parameter:
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters are
received before the next data character, an idle timeout occurs and the
buffer is closed,
generating a maskable interrupt request to the core to receive the data
from the buffer. Thus, MAX_IDL offers a way to demarcate frames. To
disable the feature, clear MAX_IDL. The bit length of an idle character
is calculated as follows: 1 + data length (5–9) + 1 (if parity is used)
+ number of stop bits (1–2). For 8 data bits, no parity, and 1 stop bit,
the character length is 10 bits
If the UART is receiving data and gets an idle character (all ones), the
channel begins counting consecutive idle characters received. If MAX_IDL
is reached, the buffer is closed and an RX interrupt is generated if not
masked. If no buffer is open, this event does not generate an interrupt
or any status information. The internal idle counter (IDLC) is reset
every time a character is received. To disable the idle sequence
function, clear MAX_IDL
The datasheet of the 16550 UART says:
Besides, for FIFO mode operation a time out mechanism is implemented.
Independently of the trigger level of the FIFO, an interrupt will be
generated if there is at least one word in the FIFO and for a time
equivalent to the transmission of four characters
- no new character has been received and
- the microprocessor has not read the RHR
To compute the time out, the current total number of bits (start, data,
parity and stop(s)) is used, together with the current baud rate (i.e.,
it depends on the contents of the LCR, DLL, DLM and PSD registers).
Christophe
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters
are received before the next data character, an idle timeout occurs
and the buffer is closed,
generating a maskable interrupt request to the core to receive the
data from the buffer. Thus, MAX_IDL offers a way to demarcate frames.
To disable the feature, clear MAX_IDL. The bit length of an idle
character is calculated as follows: 1 + data length (5–9) + 1 (if
parity is used)
+ number of stop bits (1–2). For 8 data bits, no parity, and 1 stop
bit, the character length is 10 bits
So if you have slightly bursty high speed data as its quite typical
before your change you would get one interrupt per buffer of 32 bytes,
with it you'll get a lot more interrupts.
You have two available hints about the way to set this - one of them is
the baud rate (low baud rates mean the fifo isn't a big win and the
latency is high), the other is the low_latency flag if the driver
supports the low latency feature (and arguably you can still use a
request for it as a hint even if you refuse the actual feature).
So I think a reasonable approach would be set the idle timeout down for
low baud rates or if low_latency is requested.
generated if there is at least one word in the FIFO and for a time
equivalent to the transmission of four characters
Which is a bit more reasonable than one, although problematic at low
speed (hence the fifo on/off).
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters
are received before the next data character, an idle timeout occurs
and the buffer is closed,
generating a maskable interrupt request to the core to receive the
data from the buffer. Thus, MAX_IDL offers a way to demarcate frames.
To disable the feature, clear MAX_IDL. The bit length of an idle
character is calculated as follows: 1 + data length (5–9) + 1 (if
parity is used)
+ number of stop bits (1–2). For 8 data bits, no parity, and 1 stop
bit, the character length is 10 bits
So if you have slightly bursty high speed data as its quite typical
before your change you would get one interrupt per buffer of 32 bytes,
with it you'll get a lot more interrupts.
You have two available hints about the way to set this - one of them is
the baud rate (low baud rates mean the fifo isn't a big win and the
latency is high), the other is the low_latency flag if the driver
supports the low latency feature (and arguably you can still use a
request for it as a hint even if you refuse the actual feature).
So I think a reasonable approach would be set the idle timeout down for
low baud rates or if low_latency is requested.
quoted
generated if there is at least one word in the FIFO and for a time
equivalent to the transmission of four characters
Which is a bit more reasonable than one, although problematic at low
speed (hence the fifo on/off).
What would then thing about:
* a value of 1 for all rates below 2400 (On 8250, fifo is set to 1 for
such rates)
* a value of 2 for 2400 and 4800
* a value of 4 for 9600 (which is the default on the 8250 for all rates
above 2400)
* a value of 8 for 19200
* a value of 16 for 38400 and above (on UCC_UART, maxidl is set to 16,
never 32)
Christophe
* a value of 1 for all rates below 2400 (On 8250, fifo is set to 1
for such rates)
* a value of 2 for 2400 and 4800
* a value of 4 for 9600 (which is the default on the 8250 for all
rates above 2400)
* a value of 8 for 19200
* a value of 16 for 38400 and above (on UCC_UART, maxidl is set to
16, never 32)