On Mit, 2012-04-18 at 20:20 +1000, Benjamin Herrenschmidt wrote:=20

On Wed, 2012-04-18 at 10:02 +0200, Michel D=C3=A4nzer wrote:

quoted

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quoted

GPU lockup appears to be a common problem with the radeon driver.

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It's what happens when anything goes wrong with the GPU. If it doesn't
happen with agpmode=3D-1, it's probably an AGP related coherency issue.=

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I had some success hacking the DRM to do an in_le32 from the ring head
after writing it. Just a gross hack but it seemed to help on a G5.

AFAICT radeon_ring_commit() does that already:

        DRM_MEMORYBARRIER();
        WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->=
ptr_reg_mask);
        (void)RREG32(ring->wptr_reg);

We added the readback about a decade ago. :)

I suspect there's a fundamental design issue with apple bridge in that
the CPU to memory path isn't coherent at all with the GPU to memory path
ie. even vs. cache flush instructions (ie buffers in the memory
controllers can still be out of sync).
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Darwin does some gross hacks to work around that, some of them visible
in the AGP drivers, some burried in the Apple driver, I don't know for
sure. It's possible that they end up mapping all AGP memory as cache
inhibited, but we can't do that because of our linear mapping.

We are doing that though...


--=20
Earthling Michel D=C3=A4nzer           |                   http://www.amd.c=
om
Libre software enthusiast         |          Debian, X and DRI developer