On Mar 27, 2012, at 7:17 AM, Varun Sethi wrote:

All SOC device error interrupts are muxed and delivered to the core as =

a single

MPIC error interrupt. Currently all the device drivers requiring =

access to device

errors have to register for the MPIC error interrupt as a shared =

interrupt.

=20
With this patch we add interrupt demuxing capability in the mpic =

driver, allowing

device drivers to register for their individual error interrupts. This =

is achieved

by handling error interrupts in a cascaded fashion.
=20
MPIC error interrupt is handled by the "error_int_handler", which =

subsequently demuxes

it using the EISR and delivers it to the respective drivers.=20
=20
The error interrupt capability is dependent on the MPIC EIMR register, =

which was

introduced in FSL MPIC version 4.1 (P4080 rev2). So, error interrupt =

demuxing capability

is dependent on the MPIC version and can be used for versions >=3D =

4.1.

=20
Signed-off-by: Varun Sethi <redacted>
---

This isn't quite right.  Doing the 'request_irq' on behalf of the driver =
isn't treating the error interrupts as a real cascade, in addition to =
how you are hooking things up.

I think you need to add proper irq_domain_ops, etc.  Thus when we map =
the virq the proper thing can happen.

I'd also suggest maybe thinking about pulling this code into an =
mpic_fsl.c

arch/powerpc/include/asm/mpic.h |   18 +++++
arch/powerpc/sysdev/mpic.c      |  155 =

++++++++++++++++++++++++++++++++++++++-

b/arch/powerpc/include/asm/mpic.h

Should probably be 64

/*
 * Tsi108 implementation of MPIC has many differences from the =

original one

*mpic, unsigned int ipi, u32 valu

	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
}
=20
+static inline u32 _mpic_err_read(struct mpic *mpic, unsigned int =

err_reg)

+{
+	return _mpic_read(mpic->reg_type, &mpic->err_regs, err_reg);
+}
+
+static inline void _mpic_err_write(struct mpic *mpic, unsigned int =

err_reg,

+				   u32 value)
+{
+	_mpic_write(mpic->reg_type, &mpic->err_regs, err_reg, value);
+}
+
static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned =

int tm)

*mpic, unsigned int src_no,

This seems funny, add a comment about src # and bit # being opposite.  =
Maybe do:

	eimr |=3D (1 << (31 - src));

+	mpic_err_write(err_reg_offset, eimr);
+}
+
+static void mpic_unmask_err(struct irq_data *d)
+{
+	u32 eimr;
+	struct mpic *mpic =3D mpic_from_irq_data(d);
+	unsigned int src =3D virq_to_hw(d->irq) - mpic->err_int_vecs[0];
+	unsigned int err_reg_offset =3D MPIC_INFO(ERR_INT_EIMR);
+
+	eimr =3D mpic_err_read(err_reg_offset);
+	eimr &=3D ~(0x80000000 >> src);

same as above

+	mpic_err_write(err_reg_offset, eimr);
+}
+
+static irqreturn_t error_int_handler(int irq, void *data)
+{
+	struct mpic *mpic =3D (struct mpic *) data;
+	unsigned int eisr_offset =3D MPIC_INFO(ERR_INT_EISR);
+	unsigned int eimr_offset =3D MPIC_INFO(ERR_INT_EIMR);
+	u32 eisr, eimr;
+	int errint;
+	unsigned int cascade_irq;
+
+	eisr =3D mpic_err_read(eisr_offset);
+	eimr =3D mpic_err_read(eimr_offset);
+
+	if (!(eisr & ~eimr))
+		return IRQ_NONE;
+
+	while (eisr) {
+		errint =3D __ffs(eisr);
+		cascade_irq =3D irq_linear_revmap(mpic->irqhost,
+				 mpic->err_int_vecs[31 - errint]);

Should 31, be replaced w/MPIC_MAX_ERR - 1 ?

+		WARN_ON(cascade_irq =3D=3D NO_IRQ);
+		if (cascade_irq !=3D NO_IRQ) {
+			generic_handle_irq(cascade_irq);
+		} else {
+			eimr |=3D  1 << errint;
+			mpic_err_write(eimr_offset, eimr);
+		}
+		eisr &=3D ~(1 << errint);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t =

irqnum)

+{
+	unsigned int virq;
+	unsigned int offset =3D MPIC_INFO(ERR_INT_EIMR);
+	int ret;
+
+	virq =3D irq_create_mapping(mpic->irqhost, irqnum);
+	if (virq =3D=3D NO_IRQ) {
+		pr_err("Error interrupt setup failed\n");
+		return -ENOSPC;
+	}
+
+	mpic_err_write(offset, ~0);
+
+	ret =3D request_irq(virq, error_int_handler, IRQF_NO_THREAD,
+		    "mpic-error-int", mpic);
+	if (ret) {
+		pr_err("Failed to register error interrupt handler\n");
+		return ret;
+	}
+
+	return 0;
+}
+
int mpic_set_affinity(struct irq_data *d, const struct cpumask =

*cpumask,

unsigned int virq,

struct device_node *ct,

		 */
		switch (intspec[2]) {
		case 0:
-		case 1: /* no EISR/EIMR support for now, treat as shared =

IRQ */

+			break;
+		case 1:
+			if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
+				break;
+
+			if (intspec[3] >=3D =

ARRAY_SIZE(mpic->err_int_vecs))

+				return -EINVAL;
+
+			if (!mpic->err_int_config_done) {
+				int ret;
+				ret =3D mpic_err_int_init(mpic, =

intspec[0]);

*mpic, int intvec_top)

device_node *node,

	mpic_map(mpic, mpic->paddr, &mpic->tmregs, =

MPIC_INFO(TIMER_BASE), 0x1000);

=20
	if (mpic->flags & MPIC_FSL) {
+		u32 brr1, version;
+
		/*
		 * Yes, Freescale really did put global registers in the
		 * magic per-cpu area -- and they don't even show up in =

the

device_node *node,

		 */
		mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
			 MPIC_CPU_THISBASE, 0x1000);
+
+		brr1 =3D _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
+				MPIC_FSL_BRR1);
+		version =3D brr1 & MPIC_FSL_BRR1_VER;
+
+		/* Error interrupt mask register (EIMR) is required for
+		 * handling individual device error interrupts. EIMR
+		 * was added in MPIC version 4.1.
+		 */
+		if (version >=3D 0x401) {
+			mpic->hc_err =3D mpic_err_chip;
+			mpic->hc_err.name =3D mpic->name;
+			/* Map error interrupt registers */
+			mpic_map(mpic, mpic->paddr, &mpic->err_regs,
+				 MPIC_INFO(ERR_INT_BASE), 0x1000);
+			mpic->flags |=3D MPIC_FSL_HAS_EIMR;
+		}
+
	}
=20
	/* Reset */
--=20
1.7.2.2
=20
=20
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