Hi Heiko,
On Wed, 22 Jun 2011 12:39:10 +0200
Heiko Schocher [off-list ref] wrote:
...
quoted hunk ↗ jump to hunk
diff --git a/arch/powerpc/boot/dts/a4m072.dts b/arch/powerpc/boot/dts/a4m072.dts
new file mode 100644
index 0000000..adb6746
--- /dev/null
+++ b/arch/powerpc/boot/dts/a4m072.dts
...
+ cdm@200 {
+ fsl,ext_48mhz_en = <0x0>;
+ fsl,fd_enable = <0x01>;
+ fsl,fd_counters = <0xbbbb>;
When applying this patch I've fixed these properties according to
previously added bindings (fsl,init-*-*), but one question remains:
is fd-counters value really 0xbbbb? Here, the 3rd bit in each nibble
should always be cleared as mentioned in the register description.
...
+ timer@600 {
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x600 0x80>;
+ interrupts = <1 9 0>;
I've removed above three lines as these are already in the dtsi file.
Thanks,
Anatolij