Re: [PATCH][RFC] fsldma: fix performance degradation by optimizing spinlock use.

On 11/28/2011 09:19 PM, Li Yang-R58472 wrote:

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Subject: Re: [PATCH][RFC] fsldma: fix performance degradation by optimizing
spinlock use.

On Thu, Nov 24, 2011 at 08:12:25AM +0000, Shi Xuelin-B29237 wrote:

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Hi Ira,

Thanks for your review.

After second thought, I think your scenario may not occur.
Because the cookie 20 we query must be returned by fsl_dma_tx_submit(...) in

practice.

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We never query a cookie not returned by fsl_dma_tx_submit(...).

I agree about this part.

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When we call fsl_tx_status(20), the chan->common.cookie is definitely wrote as

20 and cpu2 could not read as 19.

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This is what I don't agree about. However, I'm not an expert on CPU cache vs.
memory accesses in an multi-processor system. The section titled "CACHE
COHERENCY" in Documentation/memory-barriers.txt leads me to believe that the
scenario I described is possible.

For Freescale PowerPC, the chip automatically takes care of cache coherency.  Even if this is a concern, spinlock can't address it.

Cache coherency is not the same thing as ordering -- and spinlocks do
address ordering, because there are memory barriers in the lock
implementation.

If you're relying on some non-universal ordering guarantee that all
chips with this device make, it needs to be documented explicitly what
you're assuming and why it's valid.

-Scott