=E4=BA=8E 2011=E5=B9=B411=E6=9C=8824=E6=97=A5 16:16, Artem Bityutskiy =E5=
=86=99=E9=81=93:

On Thu, 2011-11-24 at 07:49 +0000, Li Yang-R58472 wrote:

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Subject: Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to s=

upport

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large-page Nand chip

On Thu, 2011-11-24 at 08:41 +0800, b35362@freescale.com wrote:

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+               /*
+                * Freescale FCM controller has a 2K size limitation=

 of buffer

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+                * RAM, so elbc_fcm_ctrl->buffer have to be used if =

writesize

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+                * of chip is greater than 2048.
+                * We malloc a large enough buffer (maximum page siz=

e is

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16K).

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+                */
+               elbc_fcm_ctrl->buffer =3D kmalloc(1024 * 16 + 1024,

GFP_KERNEL);

Are there NANDs with 16KiB page size?

We are not sure, but are there possibility that chip with 16K page wil=

l appear?  Or maybe we can add a MACRO for the maximum page size?

I do not know, but I know that allocating 32KiB of contiguous physical
RAM may cause unneeded memory pressure and even fail if the memory is
too fragmented. So I would not go for this unless this is necessary.

What is your suggestion ? 8k is enough ?

Did you try to look how the NAND base interface could be changed to
avoid re-allocation altogether, BTW?

This buffer is a controller-wide resource( as Scott said), I only=20
allocate buffer one time in this version.
It should be a large enough buffer for all chips.

-Liu Shuo