Re: [PATCH 03/11] powerpc/85xx: Rework PCI nodes on P1020RDB
From: Kumar Gala <hidden>
Date: 2011-10-24 14:02:06
On Oct 23, 2011, at 9:37 AM, Tabi Timur-B04825 wrote:
On Sat, Oct 22, 2011 at 4:20 PM, Kumar Gala =
[off-list ref] wrote:
quoted
* Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts=20 Are we going to be doing this for all our device trees? If so, then I think we need to document what properties the board dts should be defining when it includes a node from a dtsi. Something like this:
Yes, I intend we do this as much as possible.
dtsi:
pcie@0 {
/* dts should define 'reg' and 'ranges' */
reg =3D <0 0 0 0 0>;
#interrupt-cells =3D <1>;
=20
I suppose it's obvious that 'reg' and 'ranges' should be defined, so
this isn't the best example. But we should document if any other
properties should be defined.
=20
For example, the SSI nodes contain a bunch of SOC- and board-specific
properties.I would have hoped the bindings had made it clear already what was board = info vs what was SoC. If not, they should be clarify that in the binding specs. - k=