Re: [PATCH] powerpc/fsl-booke: Handle L1 D-cache parity error correctly on e500mc

From
Kumar Gala <hidden>
Date
2011-10-12 04:18:37
Reply to
Kumar Gala, 2011-08-27
On Aug 27, 2011, at 6:18 AM, Kumar Gala wrote:
If the L1 D-Cache is in write shadow mode the HW will auto-recover the
error.  However we might still log the error and cause a machine check
(if L1CSR0[CPE] - Cache error checking enable).  We should only treat
the non-write shadow case as non-recoverable.

Signed-off-by: Kumar Gala <redacted>
---
arch/powerpc/include/asm/reg_booke.h |    3 +++
arch/powerpc/kernel/traps.c          |    9 ++++++++-
2 files changed, 11 insertions(+), 1 deletions(-)
applied

- k
Thread (2 messages) 2 messages, 1 author, 2011-10-12
Keyboard shortcuts
hback out one level
jnext message in thread / next series-diff position
kprevious message in thread / previous series-diff position
ldrill in
Escclose help / fold thread tree
?toggle this help