RE: [PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error management registers

From: Tabi Timur-B04825
Sent: Thursday, July 21, 2011 11:59 PM
To: Xie Shaohui-B21989
Cc: linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; Jiang Kai-B18973
Subject: Re: [PATCH 3/4] powerpc/85xx: Merge PCI/PCI Express error
management registers

On Thu, Jul 21, 2011 at 5:29 AM, Shaohui Xie [off-list ref]
wrote:

quoted

+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 /* - PCIE has no this register

*/

I don't understand this sentence.

[Xie Shaohui] this patch intend to merge PCI and PCIe error management regi=
sters into a unit
Structure, some register offsets where PCI has definitions while PCIe are r=
eserved. For ex. On
MPC8536, PCI has a register ERR_CAP_DR (PCI error capture disabled register=
) at offset 0xe04,=20
But this offset is reserved in PCIe.



Best Regards,=20
Shaohui Xie