On Wed, 2011-03-09 at 14:31 +0100, Martin Schwidefsky wrote:

quoted

But if you don't also update the cpu->node memory mappings (which I
think it near impossible) what good is it to change the scheduler
topology?

=20
The memory for the different LPARs is striped over all nodes (or books as=

 we

call them). We heavily rely on the large shared cache between the books t=

o hide

the different memory access latencies.=20

Right, so effectively you don't have NUMA due to that striping. So why
then change the CPU topology? Simply create a topology without NUMA and
keep it static, that accurately reflects the memory topology.