Thread (32 messages) 32 messages, 5 authors, 2010-12-13

Re: MPC831x (and others?) NAND erase performance improvements

From: Joakim Tjernlund <hidden>
Date: 2010-12-10 12:39:07

Scott Wood [off-list ref] wrote on 2010/12/08 23:25:59:
On Wed, 8 Dec 2010 17:02:45 -0500
Mark Mason [off-list ref] wrote:
quoted
I don't think that using a software NAND controller instead of the LBC
FCM mode is all that bad.  Again, I haven't actually done it, so check
the MTD docs, but I'm pretty sure the software is meant to do that, so
it doesn't even really constitute a "fix".  Assuming that it is
supported then I doubt that configuring the NAND layer to use your
setup would be any harder than configuring the FCM.
The MTD layer supports some really simple NAND controllers, but what do
you mean by not having a controller at all?  Hooking everything up to
GPIO?  Using UPM?

There is already a UPM NAND driver, BTW.

You would lose hardware ECC and the ability to be interrupt-driven (the
latter should be possible with SW changes, using GPIO interrupts).
hmm, you think it would be possible to use one of the IRQ pins instead?
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help