Re: [PATCH v3] ppc44x:PHY fixup for USB on canyonlands board
From: Wolfgang Denk <hidden>
Date: 2010-11-26 14:23:47
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Dear Rupjyoti Sarmah, In message [ref] you wrote:
+ cpld@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "apm,ppc460ex-bcsr";This results in a mix of "amcc," and "apm," strings. Are there any plans to unify this?
quoted hunk ↗ jump to hunk
diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c new file mode 100644 index 0000000..61e80ce --- /dev/null +++ b/arch/powerpc/platforms/44x/canyonlands.c@@ -0,0 +1,120 @@ +/* + * This contain platform specific code for Canyonlands board based on + * APM ppc44x series of processors.
Canyonlands is always PPC460EX, or does it ever come with other processors as well?
+static int __init ppc44x_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ if (of_flat_dt_is_compatible(root, "amcc,canyonlands")) {
+ ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
+ return 1;
+ }
+ return 0;
+}Bad indentation.
+ /* Disable USB, through the BCSR7 bits */ + setbits8(&bcsr[7], BCSR_USB_EN); + + /* Wait for a while after reset */ + msleep(100); + + /* Enable USB here */ + clrbits8(&bcsr[7], BCSR_USB_EN); + + /* + * Configure multiplexed gpio16 and gpio19 as alternate1 output + * source after USB reset.This configuration is done through GPIO0_TSRH + * and GPIO0_OSRH bits 0:1 and 6:7. + */
Earlier versions of the patch included a delay after the clrbits8() call as well. Is it intentional that you dropped this now? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Every program has at least one bug and can be shortened by at least one instruction - from which, by induction, one can deduce that every program can be reduced to one instruction which doesn't work.