Re: [PATCH 27/27] KVM: PPC: Add Documentation about PV interface

On 02.07.2010, at 18:27, Segher Boessenkool wrote:

quoted

+To find out if we're running on KVM or not, we overlay the PVR =

register. Usually

quoted

+the PVR register contains an id that identifies your CPU type. If, =

however, you

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+pass KVM_PVR_PARA in the register that you want the PVR result in, =

the register

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+still contains KVM_PVR_PARA after the mfpvr call.
+
+	LOAD_REG_IMM(r5, KVM_PVR_PARA)
+	mfpvr	r5
+	[r5 still contains KVM_PVR_PARA]

=20
I love this part :-)

:)

=20

quoted

+	__u64 scratch3;
+	__u64 critical;		/* Guest may not get interrupts if =3D=3D =

r1 */

quoted

+	__u64 sprg0;
+	__u64 sprg1;
+	__u64 sprg2;
+	__u64 sprg3;
+	__u64 srr0;
+	__u64 srr1;
+	__u64 dar;
+	__u64 msr;
+	__u32 dsisr;
+	__u32 int_pending;	/* Tells the guest if we have an =

interrupt */

quoted

+};
+
+Additions to the page must only occur at the end. Struct fields are =

always 32

quoted

+bit aligned.

=20
The u64s are 64-bit aligned, should they always be?

That's obvious, isn't it? And the ABI only specifies u64s to be 32 bit =
aligned, no? At least that's what ld and std specify.

=20

quoted

+The "ld" and "std" instructions are transormed to "lwz" and "stw" =

instructions

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+respectively on 32 bit systems with an added offset of 4 to =

accomodate for big

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+endianness.

=20
Will this add never overflow?  Is there anything that checks for it?

It basically means that to access dar, we either do

ld  rX, DAR(0)

or

lwz rX, DAR+4(0)

=20

quoted

+mtmsrd	rX, 0		b	<special mtmsr section>
+mtmsr			b	<special mtmsr section>

=20
mtmsr rX

Nod.


Alex