Re: I2C bus clock on MPC85XX systems
From: Wolfgang Grandegger <hidden>
Date: 2009-12-22 16:19:39
From: Wolfgang Grandegger <hidden>
Date: 2009-12-22 16:19:39
Felix Radensky wrote:
Hi, Almost all MPC85XX based systems have the compatible=:"fsl-i2c" in respective i2c device tree nodes. This causes FSL i2c driver to use the following "backward compatible" values: FSR=0x31 DFSR=0x10. This is regardless of CCB clock frequency and i2c clock prescaler. On my custom MPC8536 based board with 432MHz CCB clock this results in 65KHz i2c clock frequency (checked with scope). U-Boot correctly configures the clock to 400KHz. I've fixed the problem by modifying device tree to use different compatible value, similar to what socrates board does. Is this the right approach ?
Are you aware of the properties described in "Documentation/powerpc/dts-bindings/fsl/i2c.txt": http://lxr.linux.no/#linux+v2.6.32/Documentation/powerpc/dts-bindings/fsl/i2c.txt Wolfgang.