On Nov 5, 2009, at 8:04 AM, Anton Vorontsov wrote:

On Thu, Nov 05, 2009 at 07:58:49AM -0600, Kumar Gala wrote:
[...]

quoted

--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts

@@ -40,6 +40,8 @@

			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
+			sleep = <&pmc 0x00008000	// core
+				 &pmc 0x00004000>;	// timebase

Just so I'm clear this is the devdisr bit position?

Yep, as described in the bindings.

I don't think the binding is clear that for 85xx these are DEVDISR bit  
positions for the given SoC.

- k