RE: Regression detecting memory size on PPC440EPx

Mikhail Zolotaryov wrote:

Hi Mike,
=20
you wrote:
"Row address bits : 13
DDR0_02 =3D 0x020C0E01
DDR0_42 =3D 0x00000006"
=20
Register values above define that memory has 14 row address bits. The
correct setting is (for CAS Latency =3D 3):
DDR0_42 =3D 0x01000006
=20
Best regards,
Mikhail Zolotaryov
=20

Thank you! It was a bug in U-Boot (they were encoding that register
incorrectly). I'll submit a patch to them.

Mike