Re: PPC PCI bus registers

Benjamin,

Out of order execution != out of order storage. ioremap() will give you
guarded space which means it cannot be speculatively accessed for
example, and you do get -some- guarantees but not that your stores are
going to hit the device in order, nor that your loads are going to be
performed until the CPU actually use the result of the load, which can
be delayed beyond a store.

Interesting. So IIUC if I were to use ioremap and then bit bang bus cycles using 
readN() / writeN() I would need to add memory barrier to ensure the order of the 
load and store operations does not change. Is my understanding correct? If so 
what are the recommended macros/functions for adding memory barriers, or are 
there preferred functions to use in place of ioremap() and readN()/writeN?

PS I've looked in Documentation/ in the 2.6.30 Linux kernel tree for more 
information, but I was unable to find any. If there are any example drivers or 
documentation that you know of on this topic I'd be quite interested if you 
could point me to it.

Thanks for your patience and time you've been quite helpful.

-- 
Best Regards,
________________________________________________________________
  Eddie Dawydiuk, Technologic Systems | voice:  (480) 837-5200
  16525 East Laser Drive              | fax:    (480) 837-5300
  Fountain Hills, AZ 85268            | web: www.embeddedARM.com