Re: AW: PowerPC PCI DMA issues (prefetch/coherency?)

Chris,

I noticed the following comment in pgtable.h: 

* - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
 *     doesn't support SMP. So we can use this as software bit, like
 *     DIRTY.

And _PAGE_COHERENT is not defined for the 44x (giving a compile error
when I add it the _PAGE_BASE line as you suggested). This would confirm
that the M bit is meaningless for the PPC440

Regards,
Adam


On Thu, 2009-09-03 at 09:05 +0100, Chris Pringle wrote:

Hi Adam,

If you have a look in include/asm-ppc/pgtable.h for the following section:
#ifdef CONFIG_44x
#define _PAGE_BASE    (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
#else
#define _PAGE_BASE    (_PAGE_PRESENT | _PAGE_ACCESSED)
#endif

Try adding _PAGE_COHERENT to the appropriate line above and see if that 
fixes your issue - this causes the 'M' bit to be set on the page which 
sure enforce cache coherency. If it doesn't, you'll need to check the 
'M' bit isn't being masked out in head_44x.S (it was originally masked 
out on arch/powerpc, but was fixed in later kernels when the cache 
coherency issues with non-SMP systems were resolved).

The patch I had fixed two problems on 2.6.26 for 'powerpc':
1) It stopped the 'M' bit being masked out (head_32.S)
2) It set the cache coherency ('M' bit) flag on each page table entry 
(pgtable-ppc32.h)

Hope this helps!

Cheers,
Chris

Adam Zilkie wrote:

quoted

Hi Chris,

I am having a problem similar to what you described in this discussion.
We are using the ppc arch with 2.6.24 with CONFIG_SEQUOIA with compiles
arch/ppc/kernel/head_44x.c (quite different
from /arch/powerpc/kernel/head_32.S). I would like to apply your
backporting patch to this architecture. Any help would be appreciated.

Regards,
Adam 

  

-- 
Adam Zilkie
Software Designer,
International Datacasting Corp.

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