Re: [PATCH -next] powerpc/85xx: Add support for X-ES MPC85xx boards
From: Kumar Gala <hidden>
Date: 2009-06-09 19:43:29
On Jun 9, 2009, at 1:53 PM, Nate Case wrote:
quoted hunk ↗ jump to hunk
On Mon, 2009-06-08 at 17:52 -0500, Kumar Gala wrote:quoted
quoted
+static void xes_mpc85xx_configure_l1(void) +{[snip]quoted
I'd prefer we move this into __setup_cpu_e500v1/__setup_cpu_e500v2 so its done for all processors regardless of platform.How does something like this look? Let me know and I can test and submit it separately. - Natediff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index eb4b9ad..546804f 100644--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S@@ -17,6 +17,34 @@#include <asm/cputable.h> #include <asm/ppc_asm.h> +_GLOBAL(__e500_icache_enable)
I'd prefer we test to see if the cache is enabled and if it is just return
+ mfspr r3, SPRN_L1CSR1 + oris r3, r3, L1CSR1_CPE@h + ori r3, r3, (L1CSR1_ICFI | L1CSR1_ICE) + mtspr SPRN_L1CSR1, r3 /* Enable I-Cache */ + isync + blr + +_GLOBAL(__e500_dcache_enable)
I'd prefer we test to see if the cache is enabled and if it is just return
+ msync + isync + li r3, 0 + mtspr SPRN_L1CSR0, r3 /* Disable */ + msync + isync + li r3, L1CSR0_DCFI
should probably flash reset the locks as well.
+ mtspr SPRN_L1CSR0, r3 /* Invalidate */ + msync + isync + mfspr r3, SPRN_L1CSR0 + oris r3, r3, L1CSR0_CPE@h + ori r3, r3, (L1CSR0_DCFI | L1CSR0_DCE) + msync + isync + mtspr SPRN_L1CSR0, r3 /* Enable */ + isync + blr + _GLOBAL(__setup_cpu_e20