Hi,

Now I attempt to fetch data from peripheral device to SDRAM, and it has been
successed

but how the DMA controller know the data bandwidth of src and dest.

for example, if i get a 16bits data with a 32bits bus, and other 16bits will
be set high
and data will fetched into cache line of dma, then it will be wrote to
32bits SDRAM.

You'll need to give us a little more detail. For example,
what processor are you using to perform the transaction?

Your email title says DMA of PCI bridge, however, you
mention peripheral to SDRAM. Are you using a DMA controller
on the peripheral, eg. a PCI bus master, to DMA into the
host SDRAM, or are you using a host DMA controller to
DMA over PCI into memory on the host?

Whether or not you get packing bytes when you access a
16-bit device and transfer the data to a 32-bit destination
depends on how the device is mapped. For example, a 16-bit
device can be implemented such that it responds to 8-bit,
16-bit, and 32-bit requests, but the 32-bit requests will
require more wait-states, since the device has to be
read from twice before constructing a 32-bit word to
place on the PCI bus.

Its also possible that the DMA controller can be configured
to deal with different source and destination widths. However
without knowing what processor or DMA controller you are
asking about, theres not much to say.

Cheers,
Dave