On Tue, Mar 31, 2009 at 5:07 PM, Joakim Tjernlund
[off-list ref] wrote:

Scott Wood [off-list ref] wrote on 30/03/2009 21:32:23:

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Joakim Tjernlund wrote:

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different since descriptors are in MURAM which is ioremap()ed --

though

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switching to a cacheable mapping with barriers should be a

performance

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improvement.

I always thought that MURAM was very fast. The whole reason to have

BDs in

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MURAM is that it is faster than normal RAM, at least that is what I
thought.

Yeah, on second thought it probably wouldn't be worth it. =C2=A0There's =

also

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the question of under what circumstances the QE's MURAM accesses will be

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cache-coherent.

I am a bit confused, what isn't worth it? Currently MURAM isn't used by
ucc_geth, but
it is easy to change. Swap MEM_PART_SYSTEM to MEM_PART_MURAM, however,
just
tried that and the driver stopped working. I known this worked earlier
because
I tried it and I even think I sent a patch to Leo.

What choices do we have, I see three:

1) MEM_PART_SYSTEM, as today.
2) MEM_PART_MURAM. I guess this should be uncacheable memory?
3) as gianfar, dma_alloc_coherent(). I presume this is uncacheable memory=

?

1 and 3 are the same.  All of them use cacheable memory as we have a
hardware coherency module to take care of the cache coherency problem.
 However it might be better to use dma_alloc_coherent() for the code
to be more readible.  Thanks.

- Leo