On Wed, Mar 04, 2009 at 03:04:11PM +1100, Benjamin Herrenschmidt wrote:

On Thu, 2009-02-19 at 18:21 +0100, Nick Piggin wrote:

quoted

OK, here is this patch again. You didn't think I'd let a 2% performance
improvement be forgotten? :)

Anyway, patch won't work well on architecture without lwsync, but I won't
bother fixing that kind of thing and making it merge worthy until you
guys say something positive about it.

20 runs of tbench on the G5

unpatched AVG=920.37 STD=2.36
  patched AVG=938.89 STD=3.33

(throughput in MB/s) This is a 1.9% throughput increase.

Definitely worth it believe. We could use a macro that uses michael new
improvements on the CPU features code pathing so that the isync gets
changed to lwsync on some CPUs based on the availability of it.

OK. I guess the interesting part about this is that I can't find any
IBM documentation for lwsync capable CPUs that suggest using this
pattern for acquire locking. It would be interesting to know whether
it helps other CPUs...