Hi Ben,
On Wed, 24 Sep 2008 20:17:47 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
On Wed, 2008-09-24 at 04:58 -0500, Milton Miller wrote:
quoted
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
Note also that the XICS code thus assumes, iirc, as does the cell IIC
code, that eoi is called on the -same- cpu that fetched the interrupt
initially. That assumption can be broken with IRQ threads no ?
No, the fetch and the eoi are both done in interrupt context before
the hardirq thread is woken up.
On the other hand, the mask+eoi and the unmask may well happen
on different cpus as there's only one hardirq thread per irq on
the system. Don't know if this is a problem with the XICS though.
Thanks,
Sebastien.
Ben.