WARNING: HACK - HACK - HACK
Under the RT kernel (with hardirq preemption) the eHEA driver hangs right
after booting. Fiddling with the hardirqs and softirqs priorities allows to
run a bit longer but as soon as the network gets under load, the hang
returns. After investigating, it appears that the driver is loosing interrupts.
To make a long story short, looking at the code, it appears that the XICS
maps all its interrupts to level sensitive interrupts (I don't know if it's the
reality or if it's due to an incomplete implementation - no datasheets
available to check) and use the fasteoi processing flow.
When entering the low level handler, level sensitive interrupts are masked,
then eio'd in interrupt context and then unmasked at the end of hardirq
processing.
That's fine as any interrupt comming in-between will still be processed since
the kernel replays those pending interrupts.
However, it appears that the eHEA interrupts are behaving as edge sensitive
interrupts and are routed through the XICS which process those as level
sensitive using the fasteoi handler __OR__ the XICS loses interrupts when they
are masked.
Therefore the masking done in the handler causes any interrupt happening while
in the handler to be lost.
So this patch maps the interrupts being requested through
ibmebus_request_irq() as edge sensitive interrupts (this concerns both the eHEA
and the eHCA - only users of ibmebus_request_irq()) and changes the way edge
interrupts are processed by the fasteoi handler.
It works for the eHEA, dunno for the eHCA.
So, unless all the designers of the XICS & eHEA have been shot to keep it
a secret, could someone knowledgeable shed some light on this issue.
Thanks,
Sebastien.
Not-Signed-off-by: Sebastien Dugue [off-list ref]
---
arch/powerpc/kernel/ibmebus.c | 11 ++++++++++-
kernel/irq/chip.c | 5 +++--
kernel/irq/manage.c | 9 ++++++---
3 files changed, 19 insertions(+), 6 deletions(-)
@@ -213,11 +214,19 @@ int ibmebus_request_irq(u32 ist, irq_handler_t handler,void*dev_id){unsignedintirq=irq_create_mapping(NULL,ist);+structirq_desc*desc;+intret;if(irq==NO_IRQ)return-EINVAL;-returnrequest_irq(irq,handler,irq_flags,devname,dev_id);+ret=request_irq(irq,handler,irq_flags,devname,dev_id);++desc=irq_desc+irq;+desc->status&=~(IRQ_TYPE_SENSE_MASK|IRQ_LEVEL);+desc->status|=IRQ_TYPE_EDGE_RISING;++returnret;}EXPORT_SYMBOL(ibmebus_request_irq);
Hi,
we are a bit worried about putting this into the mainstream part of non
real time linux.
There interrupts work perfectly fine, and it was a bit of a challenge to
get there for all
cases / configurations / machines.
Could you try to enable these changes only for RT-Linux via a real-time
kconfig switch?
This way we make sure we don't break the scheme for eHEA / eHCA.
Regards,
Jan-Bernd & Christoph
Sebastien Dugue [off-list ref] wrote on 15.09.2008 10:04:06:
WARNING: HACK - HACK - HACK
Under the RT kernel (with hardirq preemption) the eHEA driver hangs
right
after booting. Fiddling with the hardirqs and softirqs priorities allows
to
run a bit longer but as soon as the network gets under load, the hang
returns. After investigating, it appears that the driver is loosing
interrupts.
To make a long story short, looking at the code, it appears that the
XICS
maps all its interrupts to level sensitive interrupts (I don't know
if it's the
reality or if it's due to an incomplete implementation - no datasheets
available to check) and use the fasteoi processing flow.
When entering the low level handler, level sensitive interrupts are
masked,
then eio'd in interrupt context and then unmasked at the end of hardirq
processing.
That's fine as any interrupt comming in-between will still be processed
since
the kernel replays those pending interrupts.
However, it appears that the eHEA interrupts are behaving as edge
sensitive
interrupts and are routed through the XICS which process those as level
sensitive using the fasteoi handler __OR__ the XICS loses interruptswhen
they
are masked.
Therefore the masking done in the handler causes any interrupt
happening while
in the handler to be lost.
So this patch maps the interrupts being requested through
ibmebus_request_irq() as edge sensitive interrupts (this concerns
both the eHEA
and the eHCA - only users of ibmebus_request_irq()) and changes the way
edge
interrupts are processed by the fasteoi handler.
It works for the eHEA, dunno for the eHCA.
So, unless all the designers of the XICS & eHEA have been shot to keep
it
quoted hunk
a secret, could someone knowledgeable shed some light on this issue.
Thanks,
Sebastien.
Not-Signed-off-by: Sebastien Dugue [off-list ref]
---
arch/powerpc/kernel/ibmebus.c | 11 ++++++++++-
kernel/irq/chip.c | 5 +++--
kernel/irq/manage.c | 9 ++++++---
3 files changed, 19 insertions(+), 6 deletions(-)
@@ -439,9 +439,10 @@ handle_fasteoi_irq(unsigned int irq, struct
irq_desc *desc)
desc->status |= IRQ_INPROGRESS;
/*
* In the threaded case we fall back to a mask+eoi sequence:
+ * excepted for edge interrupts which are not masked.
*/
if (redirect_hardirq(desc)) {
- if (desc->chip->mask)
+ if (desc->chip->mask && !(desc->status & IRQ_TYPE_EDGE_BOTH))
desc->chip->mask(irq);
goto out;
}
From: Thomas Klein <hidden> Date: 2008-09-15 12:36:24
Hi,
we are a bit worried about putting this into the mainstream part of non real
time linux. There interrupts work perfectly fine, and it was a bit of a
challenge to get there for all cases / configurations / machines.
Could you try to enable these changes only for RT-Linux via a real-time
kconfig switch? This way we make sure we don't break the scheme for
eHEA / eHCA.
Regards,
Jan-Bernd, Christoph
Sebastien Dugue wrote:
quoted hunk
WARNING: HACK - HACK - HACK
Under the RT kernel (with hardirq preemption) the eHEA driver hangs right
after booting. Fiddling with the hardirqs and softirqs priorities allows to
run a bit longer but as soon as the network gets under load, the hang
returns. After investigating, it appears that the driver is loosing interrupts.
To make a long story short, looking at the code, it appears that the XICS
maps all its interrupts to level sensitive interrupts (I don't know if it's the
reality or if it's due to an incomplete implementation - no datasheets
available to check) and use the fasteoi processing flow.
When entering the low level handler, level sensitive interrupts are masked,
then eio'd in interrupt context and then unmasked at the end of hardirq
processing.
That's fine as any interrupt comming in-between will still be processed since
the kernel replays those pending interrupts.
However, it appears that the eHEA interrupts are behaving as edge sensitive
interrupts and are routed through the XICS which process those as level
sensitive using the fasteoi handler __OR__ the XICS loses interrupts when they
are masked.
Therefore the masking done in the handler causes any interrupt happening while
in the handler to be lost.
So this patch maps the interrupts being requested through
ibmebus_request_irq() as edge sensitive interrupts (this concerns both the eHEA
and the eHCA - only users of ibmebus_request_irq()) and changes the way edge
interrupts are processed by the fasteoi handler.
It works for the eHEA, dunno for the eHCA.
So, unless all the designers of the XICS & eHEA have been shot to keep it
a secret, could someone knowledgeable shed some light on this issue.
Thanks,
Sebastien.
Not-Signed-off-by: Sebastien Dugue [off-list ref]
---
arch/powerpc/kernel/ibmebus.c | 11 ++++++++++-
kernel/irq/chip.c | 5 +++--
kernel/irq/manage.c | 9 ++++++---
3 files changed, 19 insertions(+), 6 deletions(-)
@@ -213,11 +214,19 @@ int ibmebus_request_irq(u32 ist, irq_handler_t handler,void*dev_id){unsignedintirq=irq_create_mapping(NULL,ist);+structirq_desc*desc;+intret;if(irq==NO_IRQ)return-EINVAL;-returnrequest_irq(irq,handler,irq_flags,devname,dev_id);+ret=request_irq(irq,handler,irq_flags,devname,dev_id);++desc=irq_desc+irq;+desc->status&=~(IRQ_TYPE_SENSE_MASK|IRQ_LEVEL);+desc->status|=IRQ_TYPE_EDGE_RISING;++returnret;}EXPORT_SYMBOL(ibmebus_request_irq);
Hi Thomas, Jan-Bernd, Christoph,
On Mon, 15 Sep 2008 14:35:16 +0200 Thomas Klein [off-list ref] wrote:
Hi,
we are a bit worried about putting this into the mainstream part of non real
time linux.
Heck, I sure do not want this to be applied mainstream nor into any tree.
The sole purpose of this patch was to trigger some reaction from the people who
know the hardware and try to understand where the problem lies.
There interrupts work perfectly fine, and it was a bit of a
challenge to get there for all cases / configurations / machines.
Agreed, but the fact that it fails with hardirq preemption leads me to
believe (without any more knowledge about the harware) that there might be
something amiss with this driver (or the code concerning the XICS)
nevertheless.
Could you try to enable these changes only for RT-Linux via a real-time
kconfig switch?
Nope, this is just a quick hack that allows me to have a functional eHEA under
the rt kernel. I want to understand what the problem is:
- Is the eHEA really delivering level interrupts to the XICS?
- Is the XICS loosing interrupts when they are masked?
- ...?
This way we make sure we don't break the scheme for
eHEA / eHCA.
Sure, I do not want to break anything, quite the opposite in fact ;-)
Thanks,
Sebastien.
Regards,
Jan-Bernd, Christoph
Sebastien Dugue wrote:
quoted
WARNING: HACK - HACK - HACK
Under the RT kernel (with hardirq preemption) the eHEA driver hangs right
after booting. Fiddling with the hardirqs and softirqs priorities allows to
run a bit longer but as soon as the network gets under load, the hang
returns. After investigating, it appears that the driver is loosing interrupts.
To make a long story short, looking at the code, it appears that the XICS
maps all its interrupts to level sensitive interrupts (I don't know if it's the
reality or if it's due to an incomplete implementation - no datasheets
available to check) and use the fasteoi processing flow.
When entering the low level handler, level sensitive interrupts are masked,
then eio'd in interrupt context and then unmasked at the end of hardirq
processing.
That's fine as any interrupt comming in-between will still be processed since
the kernel replays those pending interrupts.
However, it appears that the eHEA interrupts are behaving as edge sensitive
interrupts and are routed through the XICS which process those as level
sensitive using the fasteoi handler __OR__ the XICS loses interrupts when they
are masked.
Therefore the masking done in the handler causes any interrupt happening while
in the handler to be lost.
So this patch maps the interrupts being requested through
ibmebus_request_irq() as edge sensitive interrupts (this concerns both the eHEA
and the eHCA - only users of ibmebus_request_irq()) and changes the way edge
interrupts are processed by the fasteoi handler.
It works for the eHEA, dunno for the eHCA.
So, unless all the designers of the XICS & eHEA have been shot to keep it
a secret, could someone knowledgeable shed some light on this issue.
Thanks,
Sebastien.
Not-Signed-off-by: Sebastien Dugue [off-list ref]
---
arch/powerpc/kernel/ibmebus.c | 11 ++++++++++-
kernel/irq/chip.c | 5 +++--
kernel/irq/manage.c | 9 ++++++---
3 files changed, 19 insertions(+), 6 deletions(-)
@@ -213,11 +214,19 @@ int ibmebus_request_irq(u32 ist, irq_handler_t handler,void*dev_id){unsignedintirq=irq_create_mapping(NULL,ist);+structirq_desc*desc;+intret;if(irq==NO_IRQ)return-EINVAL;-returnrequest_irq(irq,handler,irq_flags,devname,dev_id);+ret=request_irq(irq,handler,irq_flags,devname,dev_id);++desc=irq_desc+irq;+desc->status&=~(IRQ_TYPE_SENSE_MASK|IRQ_LEVEL);+desc->status|=IRQ_TYPE_EDGE_RISING;++returnret;}EXPORT_SYMBOL(ibmebus_request_irq);
From: Anton Vorontsov <hidden> Date: 2008-09-16 12:00:06
On Mon, Sep 15, 2008 at 03:13:32PM +0200, Sebastien Dugue wrote:
[...]
quoted
we are a bit worried about putting this into the mainstream part of non real
time linux.
Heck, I sure do not want this to be applied mainstream nor into any tree.
The sole purpose of this patch was to trigger some reaction from the people who
know the hardware and try to understand where the problem lies.
quoted
There interrupts work perfectly fine, and it was a bit of a
challenge to get there for all cases / configurations / machines.
Agreed, but the fact that it fails with hardirq preemption leads me to
believe (without any more knowledge about the harware) that there might be
something amiss with this driver (or the code concerning the XICS)
nevertheless.
quoted
Could you try to enable these changes only for RT-Linux via a real-time
kconfig switch?
Nope, this is just a quick hack that allows me to have a functional eHEA under
the rt kernel. I want to understand what the problem is:
- Is the eHEA really delivering level interrupts to the XICS?
- Is the XICS loosing interrupts when they are masked?
There is a known bug in the -rt kernels, the bug causes handlers
to lose edge interrupts.
See this patch:
http://lkml.org/lkml/2008/6/30/372
- ...?
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
Hi Anton,
On Tue, 16 Sep 2008 15:59:47 +0400 Anton Vorontsov [off-list ref] wrote:
On Mon, Sep 15, 2008 at 03:13:32PM +0200, Sebastien Dugue wrote:
[...]
quoted
quoted
we are a bit worried about putting this into the mainstream part of non real
time linux.
Heck, I sure do not want this to be applied mainstream nor into any tree.
The sole purpose of this patch was to trigger some reaction from the people who
know the hardware and try to understand where the problem lies.
quoted
There interrupts work perfectly fine, and it was a bit of a
challenge to get there for all cases / configurations / machines.
Agreed, but the fact that it fails with hardirq preemption leads me to
believe (without any more knowledge about the harware) that there might be
something amiss with this driver (or the code concerning the XICS)
nevertheless.
quoted
Could you try to enable these changes only for RT-Linux via a real-time
kconfig switch?
Nope, this is just a quick hack that allows me to have a functional eHEA under
the rt kernel. I want to understand what the problem is:
- Is the eHEA really delivering level interrupts to the XICS?
- Is the XICS loosing interrupts when they are masked?
There is a known bug in the -rt kernels, the bug causes handlers
to lose edge interrupts.
See this patch:
http://lkml.org/lkml/2008/6/30/372
Yes, I've been following that thread back then and my hack is based on your
patch. So yes, it seems to be the same problem and it lies in the way -rt handles
the fasteoi flow.
But looking at the comments from the XICS code, it seems that its wired for
level only interrupts. Therefore without any more specs, it's still not clear to
me that there's not a bug with the way the xics handles eHEA interrupts.
Are the eHEA interrupts really level interrupts? If so why do they get lost
when masked?
I just found that not masking that particular interrupt in the fasteoi path
makes the thing work!
Thanks,
Sebastien.
quoted
- ...?
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
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@@ -439,9 +439,10 @@ handle_fasteoi_irq(unsigned int irq, struct
irq_desc *desc)
desc->status |= IRQ_INPROGRESS;
/*
* In the threaded case we fall back to a mask+eoi sequence:
+ * excepted for edge interrupts which are not masked.
*/
if (redirect_hardirq(desc)) {
- if (desc->chip->mask)
+ if (desc->chip->mask && !(desc->status & IRQ_TYPE_EDGE_BOTH))
desc->chip->mask(irq);
goto out;
}
According to the specs at some point in the system the HEA IRQs have a edge
characteristic.
But since PCI-E edge and level can both be forwarded through a message
interface
(HEA is not PCI-E, it's only connected to the same internal bus, where the
PHB resides)
Anybody from the xics experts want to comment on this?
Gruss / Regards
Christoph R. & Jan-Bernd
@@ -439,9 +439,10 @@ handle_fasteoi_irq(unsigned int irq, struct
irq_desc *desc)
desc->status |= IRQ_INPROGRESS;
/*
* In the threaded case we fall back to a mask+eoi sequence:
+ * excepted for edge interrupts which are not masked.
*/
if (redirect_hardirq(desc)) {
- if (desc->chip->mask)
+ if (desc->chip->mask && !(desc->status & IRQ_TYPE_EDGE_BOTH))
desc->chip->mask(irq);
goto out;
}
According to the specs at some point in the system the HEA IRQs have a edge
characteristic.
But since PCI-E edge and level can both be forwarded through a message
interface
(HEA is not PCI-E, it's only connected to the same internal bus, where the
PHB resides)
Good to know, the problem here seems to be that the xics is using the
fasteoi flow handler, which under unconditionally masks the irq. Will have to
dig in the genirq stuff a bit more to understand what the differences are
between -rt and mainline.
Anybody from the xics experts want to comment on this?
It would be really interresting to know if the eHCA exhibits the same
problem under -rt as it's the only other user of the ibmebus.
Unfortunately I don't have the hardware to test.
Thanks,
Sebastien.
From: Christoph Raisch <hidden> Date: 2008-09-18 10:42:24
Sebastien Dugue [off-list ref] wrote on 18.09.2008 11:27:13:
It would be really interresting to know if the eHCA exhibits the same
problem under -rt as it's the only other user of the ibmebus.
Unfortunately I don't have the hardware to test.
eHCA is very close from the interrupt generation and handling perspective,
so yes, could be an issue there as well.
Gruss / Regards
Christoph Raisch
On Thu, 18 Sep 2008 12:42:05 +0200 Christoph Raisch [off-list ref] wrote:
Sebastien Dugue [off-list ref] wrote on 18.09.2008 11:27:13:
quoted
It would be really interresting to know if the eHCA exhibits the same
problem under -rt as it's the only other user of the ibmebus.
Unfortunately I don't have the hardware to test.
eHCA is very close from the interrupt generation and handling perspective,
so yes, could be an issue there as well.
Hi,
I think these are the "functional" changes that need to be included in
the ibmebus driver. We'll add a RT flag in the final version to enable
these changes only for RT-Linux for now.
Ben, can you / your team look into the implementation
of the set_irq_type functionality needed for XICS?
Regards,
Jan-Bernd & Christoph
diff -Nurp b/arch/powerpc/kernel/ibmebus.c a/arch/powerpc/kernel/ibmebus.c
@@ -216,12 +216,16 @@ int ibmebus_request_irq(u32 ist, irq_hanunsignedlongirq_flags,constchar*devname,void*dev_id){+intret;unsignedintirq=irq_create_mapping(NULL,ist);if(irq==NO_IRQ)return-EINVAL;-returnrequest_irq(irq,handler,irq_flags,devname,dev_id);+ret=request_irq(irq,handler,irq_flags,devname,dev_id);+set_irq_type(irq,IRQ_TYPE_EDGE_RISING);++returnret;}EXPORT_SYMBOL(ibmebus_request_irq);
From: Milton Miller <hidden> Date: 2008-09-24 09:58:44
Jan-Bernd wrote:
Ben, can you / your team look into the implementation
of the set_irq_type functionality needed for XICS?
I'm not volunteering to look at or implement any changes for how xics
works with generic irq, but I'm trying to understand what the rt kernel
is trying to accomplish with this statement:
On Mon Sep 15 at 18:04:06 EST in 2008, Sebastien Dugue wrote:
When entering the low level handler, level sensitive interrupts are
masked, then eio'd in interrupt context and then unmasked at the
end of hardirq processing. That's fine as any interrupt comming
in-between will still be processed since the kernel replays those
pending interrupts.
Is this to generate some kind of software managed nesting and priority
of the hardware level interrupts?
The reason I ask is the xics controller can do unlimited nesting
of hardware interrupts. In fact, the hardware has 255 levels of
priority, of which 16 or so are reserved by the hypervisor, leaving
over 200 for the os to manage. Higher numbers are lower in priority,
and the hardware will only dispatch an interrupt to a given cpu if
it is currenty at a lower priority. If it is at a higher priority
and the interrupt is not bound to a specific cpu it will look for
another cpu to dispatch it. The hardware will not re-present an
irq until the it is EOId (managed by a small state machine per
interrupt at the source, which also handles no cpu available try
again later), but software can return its cpu priority to the
previous level to recieve other interrupt sources at the same level.
The hardware also supports lazy update of the cpu priority register
when an interrupt is presented; as long as the cpu is hard-irq
enabled it can take the irq then write is real priority and let the
hw decide if the irq is still pending or it must defer or try another
cpu in the rejection scenerio. The only restriction is that the
EOI can not cause an interrupt reject by raising the priority while
sending the EOI command.
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
We used to lower the priority to allow other interrupts in, but we
realized that in addition to the questionable latency in doing so,
it only caused unlimited stack nesting and overflow without per-irq
stacks. We currently set IPIs above other irqs so we typically
only process them during a hard irq (but we return to base level
after IPI and could take another base irq, a bug).
So, Sebastien, with this information, is does the RT kernel have
a strategy that better matches this hardware?
milton
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2008-09-24 10:20:14
On Wed, 2008-09-24 at 04:58 -0500, Milton Miller wrote:
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
Note also that the XICS code thus assumes, iirc, as does the cell IIC
code, that eoi is called on the -same- cpu that fetched the interrupt
initially. That assumption can be broken with IRQ threads no ?
Ben.
From: Milton Miller <hidden> Date: 2008-09-24 11:18:47
On Sep 24, 2008, at 5:17 AM, Benjamin Herrenschmidt wrote:
On Wed, 2008-09-24 at 04:58 -0500, Milton Miller wrote:
quoted
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
Note also that the XICS code thus assumes, iirc, as does the cell IIC
code, that eoi is called on the -same- cpu that fetched the interrupt
initially. That assumption can be broken with IRQ threads no ?
There may be some implicit assumption in that we expect the cpu
priority to be returned to normal by the EOI, but there is nothing in
the hardware that requires the EOI to come from the same cpu as
accepted the interrupt for processing, with the exception of the IPI
which is per-cpu (and the only interrupt that is per-cpu).
It would probably mean adding the concept of the current cpu priority
vs interrupts and making sure we write it to hardware at irq_exit()
time when deferring the actual irq handlers.
The MPIC hardware, on the other hand, maintains a queue of pending
interrupts (It has been about a decade but the number 4-5 comes to
mind), and the hardware must receive the EOI on the cpu that took it.
I am guessing that the handling described (take level irq, mask it, eoi
it, dispatch the thread, then unmask it after processing) is a result
to work within those limitations. Do you know the cell IIC to know if
its mpic or xics in this regard?
The other unknown is the (very few) platforms that present as xics but
are really firmware on mpic. If they do a full virtual layer and don't
take shortcuts but do eoi/mask like described here they should work,
but I would not be surprised that does not hold true :-(.
milton
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2008-09-24 21:16:38
There may be some implicit assumption in that we expect the cpu
priority to be returned to normal by the EOI, but there is nothing in
the hardware that requires the EOI to come from the same cpu as
accepted the interrupt for processing, with the exception of the IPI
which is per-cpu (and the only interrupt that is per-cpu).
Well, there is one fundamental one: The XIRR register we access is
per-CPU, so if we are to return the right processor priority, we must
make sure we write the right XIRR.
Same with Cell, MPIC, actually and a few others. In general I'd say most
fast_eoi type PICs have this requirement.
It would probably mean adding the concept of the current cpu priority
vs interrupts and making sure we write it to hardware at irq_exit()
time when deferring the actual irq handlers.
I think we need something like a special -rt variant of the fast_eoi
handler that masks & eoi's in ack() before the thread is spun off, and
unmasks instead of eoi() when the irq processing is complete.
Ben.
On Thu, 25 Sep 2008 07:14:07 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
quoted
There may be some implicit assumption in that we expect the cpu
priority to be returned to normal by the EOI, but there is nothing in
the hardware that requires the EOI to come from the same cpu as
accepted the interrupt for processing, with the exception of the IPI
which is per-cpu (and the only interrupt that is per-cpu).
Well, there is one fundamental one: The XIRR register we access is
per-CPU, so if we are to return the right processor priority, we must
make sure we write the right XIRR.
That's already the case as the irq fetch (xx_xirr_info_get()) and
eoi (xx_xirr_info_set()) are both done in interrupt context, therefore on
the same cpu.
Same with Cell, MPIC, actually and a few others. In general I'd say most
fast_eoi type PICs have this requirement.
quoted
It would probably mean adding the concept of the current cpu priority
vs interrupts and making sure we write it to hardware at irq_exit()
time when deferring the actual irq handlers.
I think we need something like a special -rt variant of the fast_eoi
handler that masks & eoi's in ack() before the thread is spun off, and
unmasks instead of eoi() when the irq processing is complete.
This is what is already done in the threaded case:
- fetch + mask + eoi in interrupt context
- unmask in the thread when processing is complete.
Sebastien.
Hi Ben,
On Wed, 24 Sep 2008 20:17:47 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
On Wed, 2008-09-24 at 04:58 -0500, Milton Miller wrote:
quoted
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
Note also that the XICS code thus assumes, iirc, as does the cell IIC
code, that eoi is called on the -same- cpu that fetched the interrupt
initially. That assumption can be broken with IRQ threads no ?
No, the fetch and the eoi are both done in interrupt context before
the hardirq thread is woken up.
On the other hand, the mask+eoi and the unmask may well happen
on different cpus as there's only one hardirq thread per irq on
the system. Don't know if this is a problem with the XICS though.
Thanks,
Sebastien.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2008-09-24 21:17:59
On Wed, 2008-09-24 at 14:35 +0200, Sebastien Dugue wrote:
Hi Ben,
On Wed, 24 Sep 2008 20:17:47 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
quoted
On Wed, 2008-09-24 at 04:58 -0500, Milton Miller wrote:
quoted
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
Note also that the XICS code thus assumes, iirc, as does the cell IIC
code, that eoi is called on the -same- cpu that fetched the interrupt
initially. That assumption can be broken with IRQ threads no ?
No, the fetch and the eoi are both done in interrupt context before
the hardirq thread is woken up.
On the other hand, the mask+eoi and the unmask may well happen
on different cpus as there's only one hardirq thread per irq on
the system. Don't know if this is a problem with the XICS though.
Ok, that's the right approach then. It should work. I don't know what
the specific problems with HEA are at this stage. It doesn't seem to
make sense to implement a set_irq_type(), what would it do ? The
XICS doesn't expose any concept of interrupt type...
Ben.
On Thu, 25 Sep 2008 07:15:17 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
On Wed, 2008-09-24 at 14:35 +0200, Sebastien Dugue wrote:
quoted
Hi Ben,
On Wed, 24 Sep 2008 20:17:47 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
quoted
On Wed, 2008-09-24 at 04:58 -0500, Milton Miller wrote:
quoted
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
Note also that the XICS code thus assumes, iirc, as does the cell IIC
code, that eoi is called on the -same- cpu that fetched the interrupt
initially. That assumption can be broken with IRQ threads no ?
No, the fetch and the eoi are both done in interrupt context before
the hardirq thread is woken up.
On the other hand, the mask+eoi and the unmask may well happen
on different cpus as there's only one hardirq thread per irq on
the system. Don't know if this is a problem with the XICS though.
Ok, that's the right approach then. It should work. I don't know what
the specific problems with HEA are at this stage.
Yep, except as it behaves in way that the current -rt fasteoi flow
cannot handle.
It doesn't seem to
make sense to implement a set_irq_type(), what would it do ? The
XICS doesn't expose any concept of interrupt type...
That's what I gathered from looking at the sources.
Thanks,
Sebastien.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2008-09-25 07:25:56
On Thu, 2008-09-25 at 09:18 +0200, Sebastien Dugue wrote:
quoted
Ok, that's the right approach then. It should work. I don't know
what
quoted
the specific problems with HEA are at this stage.
Yep, except as it behaves in way that the current -rt fasteoi flow
cannot handle.
We probably need to make a special xics flow handler for -rt that does
what Milton suggested, ie, bring down the CPU priority right away and
only EOI later or something like that, instead of masking/unmasking.
I don't know what are the other potential issues with the HEA though.
Ben.
On Thu, 25 Sep 2008 17:22:41 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
On Thu, 2008-09-25 at 09:18 +0200, Sebastien Dugue wrote:
quoted
quoted
Ok, that's the right approach then. It should work. I don't know
what
quoted
the specific problems with HEA are at this stage.
Yep, except as it behaves in way that the current -rt fasteoi flow
cannot handle.
We probably need to make a special xics flow handler for -rt that does
what Milton suggested, ie, bring down the CPU priority right away
Do you mean creating a custom fasteoi handler into xics.c? Also, it's
not clear to me from looking at the code how you go about changing the
cpu priority.
and
only EOI later or something like that, instead of masking/unmasking.
I don't know what are the other potential issues with the HEA though.
Don't know either, but that I can test.
Thanks,
Sebastien.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2008-09-25 08:38:39
Do you mean creating a custom fasteoi handler into xics.c? Also, it's
not clear to me from looking at the code how you go about changing the
cpu priority.
Yup. I think the priority is the CPPR.. Milton can give you more
details, if not, I'll pick it up tomorrow when at the office.
Ben.
On Thu, 25 Sep 2008 18:36:19 +1000 Benjamin Herrenschmidt [off-list ref] wrote:
quoted
Do you mean creating a custom fasteoi handler into xics.c? Also, it's
not clear to me from looking at the code how you go about changing the
cpu priority.
Yup. I think the priority is the CPPR.. Milton can give you more
details, if not, I'll pick it up tomorrow when at the office.
Hi Milton,
On Wed, 24 Sep 2008 04:58:22 -0500 (CDT) Milton Miller [off-list ref] wrote:
Jan-Bernd wrote:
quoted
Ben, can you / your team look into the implementation
of the set_irq_type functionality needed for XICS?
I'm not volunteering to look at or implement any changes for how xics
works with generic irq, but I'm trying to understand what the rt kernel
is trying to accomplish with this statement:
On Mon Sep 15 at 18:04:06 EST in 2008, Sebastien Dugue wrote:
quoted
When entering the low level handler, level sensitive interrupts are
masked, then eio'd in interrupt context and then unmasked at the
end of hardirq processing. That's fine as any interrupt comming
in-between will still be processed since the kernel replays those
pending interrupts.
Is this to generate some kind of software managed nesting and priority
of the hardware level interrupts?
No, not really. This is only to be sure to not miss interrupts coming
from the same source that were received during threaded hardirq processing.
Some instrumentation showed that it never seems to happen in the eHEA
interrupt case, so I think we can forget this aspect.
Also, the problem only manifests with the eHEA RX interrupt. For example,
the IBM Power Raid (ipr) SCSI exhibits absolutely no problem under an RT
kernel. From this I conclude that:
IPR - PCI - XICS is OK
eHEA - IBMEBUS - XICS is broken with hardirq preemption.
I also checked that forcing the eHEA interrupt to take the non threaded
path does work.
Here is a side by side comparison of the fasteoi flow with and without hardirq
threading (sorry it's a bit wide)
fasteoi flow:
------------
Non threaded hardirq | threaded hardirq
|
interrupt context | interrupt context hardirq thread
----------------- | ----------------- --------------
|
|
clear IRQ_REPLAY and IRQ_WAITING | clear IRQ_REPLAY and IRQ_WAITING
|
increment percpu interrupt count | increment percpu interrupt count
|
if no action or IRQ_INPROGRESS or IRQ_DISABLED | if no action or IRQ_INPROGRESS or IRQ_DISABLED
|
set IRQ_PENDING | set IRQ_PENDING
|
mask | mask
|
eoi | eoi
|
done | done
|
set IRQ_INPROGRESS | set IRQ_INPROGRESS
|
|
| wakeup IRQ thread
|
| mask
|
| eoi
|
| done --
| \
| \
| \
| --> loop
|
clear IRQ_PENDING | clear IRQ_PENDING
|
call handle_IRQ_event | call handle_IRQ_event
|
| check for prempt
|
| until IRQ_PENDING cleared
|
|
clear IRQ_INPROGRESS | clear IRQ_INPROGRESS
|
if not IRQ_DISABLED | if not IRQ_DISABLED
|
unmask | unmask
|
eoi |
|
done |
the non-threaded flow does (in interrupt context):
mask
handle interrupt
unmask
eoi
the threaded flow does:
mask
eoi
handle interrupt
unmask
If I remove the mask() call, then the eHEA is no longer hanging.
The reason I ask is the xics controller can do unlimited nesting
of hardware interrupts. In fact, the hardware has 255 levels of
priority, of which 16 or so are reserved by the hypervisor, leaving
over 200 for the os to manage. Higher numbers are lower in priority,
and the hardware will only dispatch an interrupt to a given cpu if
it is currenty at a lower priority. If it is at a higher priority
and the interrupt is not bound to a specific cpu it will look for
another cpu to dispatch it. The hardware will not re-present an
irq until the it is EOId (managed by a small state machine per
interrupt at the source, which also handles no cpu available try
again later), but software can return its cpu priority to the
previous level to recieve other interrupt sources at the same level.
The hardware also supports lazy update of the cpu priority register
when an interrupt is presented; as long as the cpu is hard-irq
enabled it can take the irq then write is real priority and let the
hw decide if the irq is still pending or it must defer or try another
cpu in the rejection scenerio. The only restriction is that the
EOI can not cause an interrupt reject by raising the priority while
sending the EOI command.
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
We used to lower the priority to allow other interrupts in, but we
realized that in addition to the questionable latency in doing so,
it only caused unlimited stack nesting and overflow without per-irq
stacks. We currently set IPIs above other irqs so we typically
only process them during a hard irq (but we return to base level
after IPI and could take another base irq, a bug).
So, Sebastien, with this information, is does the RT kernel have
a strategy that better matches this hardware?
Don't think so. I think that the problem may be elsewhere as
everything is fine with PCI devices (well at least SCSI).
As I said earlier in another mail, it seems that the eHEA
is behaving as if it was generating edge interrupts which do not
support masking. Don't know.
Thanks a lot for the explanation, looks like the xics + hypervisor
combo is way more complex than I thought.
Sebastien.
From: Milton Miller <hidden> Date: 2008-09-24 16:42:23
On Sep 24, 2008, at 7:30 AM, Sebastien Dugue wrote:
Hi Milton,
On Wed, 24 Sep 2008 04:58:22 -0500 (CDT) Milton Miller
[off-list ref] wrote:
quoted
On Mon Sep 15 at 18:04:06 EST in 2008, Sebastien Dugue wrote:
quoted
When entering the low level handler, level sensitive interrupts are
masked, then eio'd in interrupt context and then unmasked at the
end of hardirq processing. That's fine as any interrupt comming
in-between will still be processed since the kernel replays those
pending interrupts.
Is this to generate some kind of software managed nesting and priority
of the hardware level interrupts?
No, not really. This is only to be sure to not miss interrupts coming
from the same source that were received during threaded hardirq
processing.
Some instrumentation showed that it never seems to happen in the eHEA
interrupt case, so I think we can forget this aspect.
I don't trust "the interrupt can never happen during hea hardirq",
because I think there will be a race between their rearming the next
interrupt and the unmask being called.
I was trying to understand why the mask and early eoi, but I guess its
to handle other more limited interrupt controllers where the interrupts
stack in hardware instead of software.
Also, the problem only manifests with the eHEA RX interrupt. For
example,
the IBM Power Raid (ipr) SCSI exhibits absolutely no problem under an
RT
kernel. From this I conclude that:
IPR - PCI - XICS is OK
eHEA - IBMEBUS - XICS is broken with hardirq preemption.
I also checked that forcing the eHEA interrupt to take the non
threaded
path does work.
For a long period of time, XICS dealt only with level interrupts.
First Micro Channel, and later PCI buses. The IPI is made level by
software conventions. Recently, EHCA, EHEA, and MSI interrupts were
added which by their nature are edge based. The logic that converts
those interrupts to the XICS layer is responsible for the resend when
no cpu can accept them, but not to retrigger after an EOI.
Here is a side by side comparison of the fasteoi flow with and
without hardirq
threading (sorry it's a bit wide)
(removed)
the non-threaded flow does (in interrupt context):
mask
handle interrupt
unmask
eoi
the threaded flow does:
mask
eoi
handle interrupt
unmask
If I remove the mask() call, then the eHEA is no longer hanging.
Hmm, I guess I'm confused. You are saying the irq does not appear if
it occurs while it is masked? Well, in that case, I would guess that
the hypervisor is checking if the irq is previously pending while it
was masked and resetting it as part of the unmask. It can't do it on
level, but can on the true edge sources. I would further say the
justification for this might be the hardware might make it pending from
some previous stale event that might result in the false interrupt on
startup were it not to do this clear.
quoted
The reason I ask is the xics controller can do unlimited nesting
of hardware interrupts. In fact, the hardware has 255 levels of
priority, of which 16 or so are reserved by the hypervisor, leaving
over 200 for the os to manage. Higher numbers are lower in priority,
and the hardware will only dispatch an interrupt to a given cpu if
it is currenty at a lower priority. If it is at a higher priority
and the interrupt is not bound to a specific cpu it will look for
another cpu to dispatch it. The hardware will not re-present an
irq until the it is EOId (managed by a small state machine per
interrupt at the source, which also handles no cpu available try
again later), but software can return its cpu priority to the
previous level to recieve other interrupt sources at the same level.
The hardware also supports lazy update of the cpu priority register
when an interrupt is presented; as long as the cpu is hard-irq
enabled it can take the irq then write is real priority and let the
hw decide if the irq is still pending or it must defer or try another
cpu in the rejection scenerio. The only restriction is that the
EOI can not cause an interrupt reject by raising the priority while
sending the EOI command.
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
We used to lower the priority to allow other interrupts in, but we
realized that in addition to the questionable latency in doing so,
it only caused unlimited stack nesting and overflow without per-irq
stacks. We currently set IPIs above other irqs so we typically
only process them during a hard irq (but we return to base level
after IPI and could take another base irq, a bug).
So, Sebastien, with this information, is does the RT kernel have
a strategy that better matches this hardware?
Don't think so. I think that the problem may be elsewhere as
everything is fine with PCI devices (well at least SCSI).
Those are true level sources, and not edge.
As I said earlier in another mail, it seems that the eHEA
is behaving as if it was generating edge interrupts which do not
support masking. Don't know.
(I wrote this next paragraph before parsing the "remove mask and it
works" / I'm confused paragraph above, so it may not be a problem).
These sources are truly edge. Once you do an EOI you are taking
responsibility to do the replay yourself. In your threaded case, you
EOI and therefore the hardware will arm for the next event. When you
add the mask, the delivery is deferred until it is unmasked at the end
of your EOI loop. When you do not, the new interrupt may come in but
you just EOI it but do not tell the running thread that it happened,
then you are dropping the irq event. Since the source is truly edge,
there is no hardware replay and the interrupt is lost.
(I think the pci express gigabit is one of the few msi interrupt
adapters that both IBM and Linux support).
Thanks a lot for the explanation, looks like the xics + hypervisor
combo is way more complex than I thought.
While the hypervisor adds a bit of path length (an hcall vs a single
mmio access for get_irq/eoi with multiple priority irq nesting), the
model is no more or less complicated than native xics.
The path lengh for mask and unmask is always VERY slow and single
threaded global lock and single context in xics. It is designed and
tuned to run at driver startup and shutdown (and adapter reset and
reinitalize during pci error processing), not during normal irq
processing.
The XICS hardware implicitly masks the specific source as part of
interrupt ack (get_irq), and implicitly undoes this mask at eoi. In
addition, it helps to manage the cpu priority by supplying the previous
priority as part of the get_irq process and providing for the priority
to be restored (lowered only) as part of the eoi. The hardware does
support setting the cpu priority independently.
We should only be using this implicit masking for xics, and not the
explicit masking for any normal interrupt processing. I don't know if
this means making the mask/unmask setting a bit in software, and the
enable/disable to actually call what we do now on mask/unmask, or if it
means we need a new flow type on real time.
While call to mask and unmask might work on level interrupts, its
really slow and will limit performance if done on every interrupt.
the non-threaded flow does (in interrupt context):
mask
handle interrupt
unmask
eoi
the threaded flow does:
mask
eoi
handle interrupt
unmask
I think the flows we want on xics are:
(non-threaded)
getirq (implicit source specific mask until eoi)
handle interrupt
eoi (implicit cpu priority restore)
(threaded)
getirq (implicit source specific mask until eoi)
explicit cpu priority restore
handle interrupt
eoi (implicit cpu priority restore to same as explicit level)
Where the cpu priority restore allows receiving other interrupts of the
same priority from the hardware.
So I guess the question is can the rt kernel interrupt processing take
advantage of xics auto mask, or does someone need to write state
tracking in the xics code to work around this, changing mask under
interrupt to "defer eoi to unmask" (which I can not see as clean, and
having shutdown problems).
milton
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2008-09-24 21:23:55
On Wed, 2008-09-24 at 11:42 -0500, Milton Miller wrote:
I was trying to understand why the mask and early eoi, but I guess its
to handle other more limited interrupt controllers where the interrupts
stack in hardware instead of software.
No Milton, we must do it that way, because the EOI must be done on the
right CPU even on XICS, or we won't get the CPU priority back properly.
Ben.
From: Milton Miller <hidden> Date: 2008-09-25 03:56:33
On Sep 24, 2008, at 4:16 PM, Benjamin Herrenschmidt wrote:
On Wed, 2008-09-24 at 11:42 -0500, Milton Miller wrote:
quoted
I was trying to understand why the mask and early eoi, but I guess its
to handle other more limited interrupt controllers where the
interrupts
stack in hardware instead of software.
No Milton, we must do it that way, because the EOI must be done on the
right CPU even on XICS, or we won't get the CPU priority back properly.
Ben and I had a online chat, and he pointed out I needed to be more
specific in saying what I was thinking.
quoted
I think the flows we want on xics are:
(non-threaded)
getirq (implicit source specific mask until eoi)
handle interrupt
eoi (implicit cpu priority restore)
(threaded)
getirq (implicit source specific mask until eoi)
explicit cpu priority restore
handle interrupt
eoi (implicit cpu priority restore to same as explicit level)
cpu takes interrupt, checks soft disabled
if so,
set hard disabled
else
call get_irq
if threaded
write cppr to restore this cpu irq dispatch state to non-interrupt
mark irq thread as irq pending
else
handle interrupt
eoi (cppr = base)
irq thread will
handle interrupt
eoi
wait for marked pending again
The part Ben did not follow was that the cppr write to base priority is
done by the interrupted cpu (like the mask and eoi in the current flow)
and only the final eoi (where the mask is in the existing flow) is done
on which ever cpu happens to run the irq thread.
(optional) As I was discussing with Paul, when taking an irq when
soft-disabled but still hard enabled, it is possible to write the cppr
such that it would reject the pending irq and have it be considered for
dispatch to another cpu. But it would increase pathlength on both the
go-to-hard-disabled and return-from-hard-disabled and the hardware will
have some latency as it will likely send it back to the io source until
it retrys, so we would only want to do this if the hard-disable period
is sufficiently long.
milton
On Wed, 24 Sep 2008 11:42:15 -0500 Milton Miller [off-list ref] wrote:
On Sep 24, 2008, at 7:30 AM, Sebastien Dugue wrote:
quoted
Hi Milton,
On Wed, 24 Sep 2008 04:58:22 -0500 (CDT) Milton Miller
[off-list ref] wrote:
quoted
On Mon Sep 15 at 18:04:06 EST in 2008, Sebastien Dugue wrote:
quoted
When entering the low level handler, level sensitive interrupts are
masked, then eio'd in interrupt context and then unmasked at the
end of hardirq processing. That's fine as any interrupt comming
in-between will still be processed since the kernel replays those
pending interrupts.
Is this to generate some kind of software managed nesting and priority
of the hardware level interrupts?
No, not really. This is only to be sure to not miss interrupts coming
from the same source that were received during threaded hardirq
processing.
Some instrumentation showed that it never seems to happen in the eHEA
interrupt case, so I think we can forget this aspect.
I don't trust "the interrupt can never happen during hea hardirq",
because I think there will be a race between their rearming the next
interrupt and the unmask being called.
So do I, it was just to make sure I was not hit by another interrupt while
handling the previous one and thus reduce the number of hypothesis.
I sure do not say that it cannot happen, just that that path is not taken
when I have the eHEA hang.
I was trying to understand why the mask and early eoi, but I guess its
to handle other more limited interrupt controllers where the interrupts
stack in hardware instead of software.
quoted
Also, the problem only manifests with the eHEA RX interrupt. For
example,
the IBM Power Raid (ipr) SCSI exhibits absolutely no problem under an
RT
kernel. From this I conclude that:
IPR - PCI - XICS is OK
eHEA - IBMEBUS - XICS is broken with hardirq preemption.
I also checked that forcing the eHEA interrupt to take the non
threaded
path does work.
For a long period of time, XICS dealt only with level interrupts.
First Micro Channel, and later PCI buses. The IPI is made level by
software conventions. Recently, EHCA, EHEA, and MSI interrupts were
added which by their nature are edge based. The logic that converts
those interrupts to the XICS layer is responsible for the resend when
no cpu can accept them, but not to retrigger after an EOI.
OK
quoted
Here is a side by side comparison of the fasteoi flow with and
without hardirq
threading (sorry it's a bit wide)
(removed)
quoted
the non-threaded flow does (in interrupt context):
mask
Whoops, my bad, in the non threaded case, there's no mask at all, only an
unmask+eoi at the end, maybe that's an oversight!
quoted
handle interrupt
unmask
eoi
the threaded flow does:
mask
eoi
handle interrupt
unmask
If I remove the mask() call, then the eHEA is no longer hanging.
Hmm, I guess I'm confused. You are saying the irq does not appear if
it occurs while it is masked?
Looks like it is, but I cannot say for sure, the only observable effect
is that I do not get any more interrupts coming from the eHEA.
Well, in that case, I would guess that
the hypervisor is checking if the irq is previously pending while it
was masked and resetting it as part of the unmask. It can't do it on
level, but can on the true edge sources. I would further say the
justification for this might be the hardware might make it pending from
some previous stale event that might result in the false interrupt on
startup were it not to do this clear.
quoted
quoted
The reason I ask is the xics controller can do unlimited nesting
of hardware interrupts. In fact, the hardware has 255 levels of
priority, of which 16 or so are reserved by the hypervisor, leaving
over 200 for the os to manage. Higher numbers are lower in priority,
and the hardware will only dispatch an interrupt to a given cpu if
it is currenty at a lower priority. If it is at a higher priority
and the interrupt is not bound to a specific cpu it will look for
another cpu to dispatch it. The hardware will not re-present an
irq until the it is EOId (managed by a small state machine per
interrupt at the source, which also handles no cpu available try
again later), but software can return its cpu priority to the
previous level to recieve other interrupt sources at the same level.
The hardware also supports lazy update of the cpu priority register
when an interrupt is presented; as long as the cpu is hard-irq
enabled it can take the irq then write is real priority and let the
hw decide if the irq is still pending or it must defer or try another
cpu in the rejection scenerio. The only restriction is that the
EOI can not cause an interrupt reject by raising the priority while
sending the EOI command.
The per-interrupt mask and unmask calls have to go through RTAS, a
single-threaded global context, which in addition to increasing
path length will really limit scalability. The interrupt controller
poll and reject facilities are accessed through hypervisor calls
which are comparable to a fast syscall, and parallel to all cpus.
We used to lower the priority to allow other interrupts in, but we
realized that in addition to the questionable latency in doing so,
it only caused unlimited stack nesting and overflow without per-irq
stacks. We currently set IPIs above other irqs so we typically
only process them during a hard irq (but we return to base level
after IPI and could take another base irq, a bug).
So, Sebastien, with this information, is does the RT kernel have
a strategy that better matches this hardware?
Don't think so. I think that the problem may be elsewhere as
everything is fine with PCI devices (well at least SCSI).
Those are true level sources, and not edge.
Right.
quoted
As I said earlier in another mail, it seems that the eHEA
is behaving as if it was generating edge interrupts which do not
support masking. Don't know.
(I wrote this next paragraph before parsing the "remove mask and it
works" / I'm confused paragraph above, so it may not be a problem).
These sources are truly edge. Once you do an EOI you are taking
responsibility to do the replay yourself. In your threaded case, you
EOI and therefore the hardware will arm for the next event. When you
add the mask, the delivery is deferred until it is unmasked at the end
of your EOI loop. When you do not, the new interrupt may come in but
you just EOI it but do not tell the running thread that it happened,
then you are dropping the irq event. Since the source is truly edge,
there is no hardware replay and the interrupt is lost.
(I think the pci express gigabit is one of the few msi interrupt
adapters that both IBM and Linux support).
quoted
Thanks a lot for the explanation, looks like the xics + hypervisor
combo is way more complex than I thought.
While the hypervisor adds a bit of path length (an hcall vs a single
mmio access for get_irq/eoi with multiple priority irq nesting), the
model is no more or less complicated than native xics.
That may be, but I'm only looking at the code (read no specifications at hand)
and it looks like a black box to me.
The path lengh for mask and unmask is always VERY slow and single
threaded global lock and single context in xics. It is designed and
tuned to run at driver startup and shutdown (and adapter reset and
reinitalize during pci error processing), not during normal irq
processing.
Now, that is quite interesting then. Those mask() and unmask() should then
be called shutdown() and startup() and not at each interrupt or am I
misunderstanding you.
The XICS hardware implicitly masks the specific source as part of
interrupt ack (get_irq), and implicitly undoes this mask at eoi. In
addition, it helps to manage the cpu priority by supplying the previous
priority as part of the get_irq process and providing for the priority
to be restored (lowered only) as part of the eoi. The hardware does
support setting the cpu priority independently.
This confirms, then, that the mask and unmask methods should be empty
for the xics.
We should only be using this implicit masking for xics, and not the
explicit masking for any normal interrupt processing.
OK
I don't know if
this means making the mask/unmask setting a bit in software,
Used by whom?
and the
enable/disable to actually call what we do now on mask/unmask, or if it
means we need a new flow type on real time.
Maybe a new flow type is not necessary considering what you said.
While call to mask and unmask might work on level interrupts, its
really slow and will limit performance if done on every interrupt.
quoted
the non-threaded flow does (in interrupt context):
mask
Same Whoops, no mask is done in the non threaded case
I think the flows we want on xics are:
(non-threaded)
getirq (implicit source specific mask until eoi)
handle interrupt
eoi (implicit cpu priority restore)
Yep
(threaded)
getirq (implicit source specific mask until eoi)
explicit cpu priority restore
^
How do you go about doing that? Still not clear to me.
handle interrupt
eoi (implicit cpu priority restore to same as explicit level)
Where the cpu priority restore allows receiving other interrupts of the
same priority from the hardware.
So I guess the question is can the rt kernel interrupt processing take
advantage of xics auto mask,
It should, but even mainline could benefit from it I guess.
or does someone need to write state
tracking in the xics code to work around this, changing mask under
interrupt to "defer eoi to unmask" (which I can not see as clean, and
having shutdown problems).
Thanks a lot Milton for those explanations,
Sebastien.