Michael Ellerman writes:
The PCI bridge representing the PCIE root complex on Axon, contains device
BARs for a memory range and ROM that define inbound accesses. This confuses
the kernel resource management code, the resources need to be hidden when
Axon is a host bridge.
Since you didn't say, I assume this isn't needed for 2.6.25... right?
(Please, everybody, if you want a patch in 2.6.25, put something in the
subject line to indicate that, such as a [2.6.25] tag.)
Paul.