[PATCH 2/2] [POWERPC] Add L2 cache node to AMCC Taishan dts file

This patch adds the L2 cache node to the Taishan 440GX dts file.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/powerpc/boot/dts/taishan.dts     |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 8278068..d0bff33 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts

@@ -104,6 +104,16 @@
 		// FIXME: anything else?
 	};
 
+	L2C0: l2c@30 {
+		compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+		dcr-reg = <20 8			/* Internal SRAM DCR's */
+			   30 8>;		/* L2 cache DCR's */
+		cache-line-size = <20>;		/* 32 bytes */
+		cache-size = <40000>;		/* L2, 256K */
+		interrupt-parent = <&UIC2>;
+		interrupts = <17 1>;
+	};
+
 	plb {
 		compatible = "ibm,plb-440gx", "ibm,plb4";
 		#address-cells = <2>;

-- 
1.5.4.4

The unit address is based on the _first_ entry in "reg".  No2 this
is "dcr-reg", but you don't really want to be more incompatible than
necessary...


Segher

On Tue, Mar 18, 2008 at 02:37:46PM +0100, Stefan Roese wrote:

A node with no reg property shouldn't have a unit address.

Now.. usually cache nodes are given as descendents of the CPU node.
In this case you have the DCR control registers though, so I guess
this is representing a control interface rather than the cache
itself.  Hrm.. not really sure how to do this.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

On Wednesday 19 March 2008, David Gibson wrote:

On Tue, Mar 18, 2008 at 02:37:46PM +0100, Stefan Roese wrote:

quoted

This patch adds the L2 cache node to the Taishan 440GX dts file.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/powerpc/boot/dts/taishan.dts     |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/taishan.dts

b/arch/powerpc/boot/dts/taishan.dts index 8278068..d0bff33 100644

--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts

@@ -104,6 +104,16 @@
 		// FIXME: anything else?
 	};

+	L2C0: l2c@30 {

A node with no reg property shouldn't have a unit address.

OK, I'll remove the unit address.

quoted

+		compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+		dcr-reg = <20 8			/* Internal SRAM DCR's */
+			   30 8>;		/* L2 cache DCR's */
+		cache-line-size = <20>;		/* 32 bytes */
+		cache-size = <40000>;		/* L2, 256K */
+		interrupt-parent = <&UIC2>;
+		interrupts = <17 1>;
+	};

Now.. usually cache nodes are given as descendents of the CPU node.
In this case you have the DCR control registers though, so I guess
this is representing a control interface rather than the cache
itself.  Hrm.. not really sure how to do this.

So should I change the location then?

Best regards,
Stefan

On Tuesday 18 March 2008, Segher Boessenkool wrote:

quoted

+	L2C0: l2c@30 {
+		compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+		dcr-reg = <20 8			/* Internal SRAM DCR's */
+			   30 8>;		/* L2 cache DCR's */

The unit address is based on the _first_ entry in "reg".

I'll remove the unit address.

No2 this 
is "dcr-reg", but you don't really want to be more incompatible than
necessary...

Sorry, I'm not sure what you're trying to tell me here.

Best regards,
Stefan