On Thu, 2007-10-11 at 09:12 -0500, Kumar Gala wrote:
On Oct 11, 2007, at 6:46 AM, Paul Mackerras wrote:
quoted
In testing the new clocksource and clockevent code on a PPC601
processor, I discovered that the clockevent multiplier value for the
decrementer clockevent was overflowing. Because the RTCL register in
the 601 effectively counts at 1GHz (it doesn't actually, but it
increases by 128 every 128ns), and the shift value was 32, that meant
the multiplier value had to be 2^32, which won't fit in an unsigned
long on 32-bit. The same problem would arise on any platform where
the timebase frequency was 1GHz or more (not that we actually have any
such machines today).
do you still have a 601 running somewhere?
On my desk :-) (and he also has a 601 card for the 7500 iirc)
/me remembers to revive his dual 604 8500 one of these days.
Ben.