In message [ref] you wrote:
The problem is that I can't seem to get any interrupts
(not ata, not bestcomm task), when setting up MWDMA/UDMA mode.
First, please check the errata. There are some issues in this area -
one involves the ATA controller not handling automatic pause for DMA
transfers (controller will corrupt FIFO data when there is any sig-
nificant transfer load - system freezes, kernel crashes); another one
is erratum 158: "ATA interrupt is not affected by FIFO errors."
Best regards,
Wolfgang Denk
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DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
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