Re: Fix small race in 44x tlbie function

On Wed, Aug 08, 2007 at 05:11:09PM -0500, Hollis Blanchard wrote:

On Wed, 2007-08-08 at 16:29 -0500, Josh Boyer wrote:

quoted

On Wed, 8 Aug 2007 20:43:25 +0000 (UTC)
Hollis Blanchard [off-list ref] wrote:

quoted

On Tue, 07 Aug 2007 14:20:50 +1000, David Gibson wrote:

quoted

This patch fixes the problem in both arch/ppc and arch/powerpc by
inhibiting interrupts (even critical and debug interrupts) across the
relevant instructions.

How could a critical or debug interrupt modify the contents of MMUCR?

Interrupts from UICs can be configured as critical.  If one of those
triggers, (or any other CE triggers) and causes a tlb miss, you have a
race.  The watchdog timer interrupt also is a CE IIRC.

By "causes a tlb miss", you mean the interrupt handler associated with
the critical-priority UIC interrupt performs MMIO which causes a TLB
miss? Regular code couldn't cause a TLB miss AFAICS, since the kernel is
always mapped, and an interrupt handler doesn't access userspace.

Yes.

josh