Hi, Segher,=20
=20

quoted

+    - #address-cells : Address representation for=20

"rapidio" devices.

quoted

+      This field represents the number of cells needed to represent
+      the RapidIO address of the registers.  For=20

supporting more than

quoted

+      32-bits RapidIO address, this field should be <2>.
+      See 1) above for more details on defining #address-cells.

=20
What does the RapidIO standard say about number of address
bits?  You want to follow that, so all RapidIO devices can
use the same #address-cells, not just the FSL ones.  Also,
are there different kinds of address spaces on the bus, or
is it just one big memory-like space?
=20
=20

I've checked the specification of RapidIO. The supporting of RapidIO
extended address modes are 66, 50 and 34 bit.
The Freescale's silicons is only support 34 bit address now.
Do you mean I should not use words -- 'should be <2>'?
The #address-cells should be assigned according the address mode
supported by silicon.

Thanks!
Wei.