The current 85xxCDS restart code fails to reset the PCI bus which can
lead to odd behavior after the restart. This patch uses the VIA Super
Southbridge to perform a PCI reset which will reset the entire system.
NOTE: Since the VIA chip is behind a PCI-to-PCI bridge which can be
disabled with a switch setting, it may not be possible to perform the
PCI bus reset. In this case, the code defaults to the previous restart
mechanism.
Signed-off-by: Randy Vinson <redacted>
---
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 26 ++++++++++++++++++++++++++
1 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 431aaa2..f1eaf07 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -62,6 +62,28 @@ static volatile u8 *cadmus;
extern int mpc85xx_pci2_busno;
+static void mpc85xx_cds_restart(char *cmd)
+{
+ struct pci_dev *dev;
+ u_char tmp;
+
+ if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
+ NULL))) {
+
+ /* Use the VIA Super Southbridge to force a PCI reset */
+ pci_read_config_byte(dev, 0x47, &tmp);
+ pci_write_config_byte(dev, 0x47, tmp | 1);
+
+ pci_dev_put(dev);
+ }
+
+ /*
+ * We should only get here if the P2P bridge is disabled. In that
+ * case, just use the default reset.
+ */
+ mpc85xx_restart(NULL);
+}
+
static int mpc85xx_exclude_device(u_char bus, u_char devfn)
{
if (bus == 0 && PCI_SLOT(devfn) == 0)@@ -327,7 +349,11 @@ define_machine(mpc85xx_cds) {
.init_IRQ = mpc85xx_cds_pic_init,
.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
.get_irq = mpic_get_irq,
+#ifdef CONFIG_PCI
+ .restart = mpc85xx_cds_restart,
+#else
.restart = mpc85xx_restart,
+#endif
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};--
1.5.0.GIT