Re: System Ace booting (or not) question

Hi,

  We got it to load into DDR ram, based on a comment you made earlier about
how the system ace works.

  In our  genace.opt file (the one we made ourselves), an engineer had put
-debugdevice devicenr 1 cpunr 2

  It turns out that the last "debugdevice" being used is the one that the
system ace chip uses to gain control of to download the elf file into ram.
We had picked the cpu that was not tied to the plb bus, so it could not
write to ram.  The system ace did not care and did not error out.

  Once we set it to
-debugdevice devicenr 1 cpunr 1

  then it loaded into ram and tried. to execute.  We are now having DDR ram
problems, we are trying to solve those problems.

thanks again for your help!

wade


On 1/23/07, linux-ppc@eurotel.it [off-list ref] wrote:

Hi Wade,
we made our board from scratch, there are two FPGA, one FX12 and one SX35,
loaded with system ace,Montavista Linux and everything is ok.
Is the JTAG chain in the correct sequence?
are there in your board only one fpga or there is a chain with two fpga?
if yes the Xilinx documentation with genace.tcl fails to concatenate two
fpga files.
also verify the tools errors manually executing the genace.tcl commands;
they are not so difficult to understand.
also verify that bootlloop code is loaded into the fabric ram.
keep in mind that your memory is to be loaded via JTAG command, so if FPGA
load correctly and DDR is working, then there is no reason to have DDR load
failure.
regards


 *"Wade Maxfield" [off-list ref]*
Sent by: linuxppc-embedded-bounces+linux-ppc=eurotel.it@ozlabs.org

05/01/2007 17.23
  To
christophe.alayrac@cresitt.com  cc
ppc [off-list ref]  Subject
Re: System Ace booting (or not) question






Hi Alayrac,

 Thank you for your reply.

 No, there is no bus error.

 The memory map of our design matches the ML403 as regards the DDR ram.
 We are just trying to get the code into external DDR Ram.

 The code start address is specified in the elf file, and lists correctly
on the screen as the genace script executes.

 The code in zImage.elf is compiled to the DDR space, and so should load
there.   The genace script prints out the code will load there when it runs
and places
the .elf file into the system.  The system.ace file is 10 megabytes after
the zImage.elf code is put into it.  when doing only the internal block
ram load, the system.ace
file is only 2.8 megabytes in size.


thanks again,
wade




On 1/5/07, *alayrac christophe* <*christophe.alayrac@cresitt.com*[off-list ref]> wrote:
High Wade,

Does systemace comes out with a bus error? (Red led on ML403 board)?

If yes may be its because the memory map of your design did not fit with
ML403 ones and that SystemaAce try to load kernel image in a non ram
place.

you may have to specify the code start address to the genace.tcl script
to generate properly the ace file. (it should be something like
start_address 0xYOURADDR in the opt file)

Have you tried to download the kernel image through JTAG?

You can also try to compile a standalone code in DDR space (not BRAM as
describe in your email) an try to make an ace file with it.

regards

Chris

Le vendredi 05 janvier 2007 à 09:20 -0600, Wade Maxfield a écrit :

quoted

  I'm very new to System Ace, and this is probably a stupid question.

  We were able, with the Monta Vista Linux to get a system.ace with a
zImage.elf linux file to boot on an ml403 board.  The system ace chip
seemed to copy the zImage.elf into DDR ram, and the system booted.  No
block ram used.

   We created a board with an xf60 and a system ace chip on it and
created a system.ace file.  The xilinx loads, but the zImage.elf does
not copy into ddr ram.  We ran the testfatfs code and read from and
wrote to the compact flash on the system ace chip, verifying the files
through a compact flash adaptor on a pc.

   We created a memory test using the ppc and were able (after some
wiring changes and other headaches) to prove the ddr ram works.  There
is enough of it to support linux (64 meg), and testing all 64 million
locations with various fixed and incrementing patterns proves it
works.

   However, we could not get the external ram to load up with the
linux zImage.elf file. When this failed, we created a system.ace file
with two elf's in it, one for linux, one for a memory read/write
tester in block ram.

  It appears the system ace chip loads the info into block ram just
fine, and our memory test executes.  However, our ddr ram has nothing
in it.  We reversed the order of the elf files, and that still did not
help.

  Do we need a helper CPLD on this board to accomplish what the ML403
accomplishes?  Or do we need to do a boot loader in code?  If we need
to do a boot loader, how come the Monta Vista linux doesn't need one
on the ml403 board?  I've been googling and scouring the Xilinx site,
but I've achieved nothing but a few less hairs on my head.

  I've already asked Monta Vista this question, and they quoted
verbatim the page from the xilinx manual, which is a generic answer to
the specific question.  Even if the xilinx manual is the answer, we
aren't seeing the results the manual implies we will see.

  Can someone give me a clue?

thanks,
wade

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