[PATCH] # ppc: ppc4xx_set_src/dst_addr were only correct for DMA0

[PATCH] # ppc: ppc4xx_set_src/dst_addr were only correct for DMA0

The DCR-register numbers for DMA1-DMA3 were wrongly corrected.

Signed-off-by: Niklaus Giger <redacted>
---
 arch/ppc/syslib/ppc4xx_dma.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/ppc/syslib/ppc4xx_dma.c b/arch/ppc/syslib/ppc4xx_dma.c
index 1cb68a6..26b2ddf 100644
--- a/arch/ppc/syslib/ppc4xx_dma.c
+++ b/arch/ppc/syslib/ppc4xx_dma.c

@@ -47,9 +47,9 @@ ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr)
 	}
 
 #ifdef PPC4xx_DMA_64BIT
-	mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
+	mtdcr(DCRN_DMASAH0 + dmanr * 0x8, (u32)(src_addr >> 32));
 #else
-	mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
+	mtdcr(DCRN_DMASA0 + dmanr * 0x8, (u32)src_addr);
 #endif
 }
 

@@ -62,9 +62,9 @@ ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr)
 	}
 
 #ifdef PPC4xx_DMA_64BIT
-	mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32));
+	mtdcr(DCRN_DMADAH0 + dmanr * 0x8, (u32)(dst_addr >> 32));
 #else
-	mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr);
+	mtdcr(DCRN_DMADA0 + dmanr * 0x8, (u32)dst_addr);
 #endif
 }

On Saturday 20 January 2007 00:02, Niklaus Giger wrote:

DCRN_DMASAH0 + dmanr*2

to

DCRN_DMASAH0 + dmanr * 0x8

Wouln't it be possible to give DCRN_DMASAH0 such an type that
DCRN_DMASAH0 + dmanr
would do? Or even better
DCRN_DMASAH[dmanr]

BTW this code looks suspicious, how will the 64BIT dma
ever work? Only highest 32 bits are stored...

PPC should really try to move toward the generic interface...

/RogerL