On Sat, 2006-12-02 at 22:15 +1100, Benjamin Herrenschmidt wrote:

I think we are hitting a livelock due to both CPUs trying to perform an
atomic operation on the same cache line (or same variable even).

I agree.

Can you remind me what CPU this on precisely ? I know that for some
CPUs like 970's, Apple code has some weirdo workarounds around atomic
ops involving forcing a mispredict when the stwcx. fails ... but if both
CPUs are following the exact same pattern, I can't see another way out
but an interrupt, unless something in the bus protocol can prevent such
livelocks...

It's a pair of 7448s in MPX bus mode, with a Tsi109 host bridge.

-- 
Adrian Cox [off-list ref]