-----Original Message-----
From: Liu Dave-r63238
Sent: Wednesday, August 30, 2006 10:27 AM
To: Liu Dave-r63238; Li Yang-r58472; linuxppc-embedded@ozlabs.org;
linuxppc-dev@ozlabs.org
Subject: RE: atomic operations in user space
=20

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[snip]

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I surely know all the theories you mentioned clearly.  But

please do

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look at the case I gave.  Correct me if I missed anything.  Thanks

All the lwarx and stwcx operate on the same address.

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Task A		Task B
lwarx

// Get RESERVATION

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			......
			lwarx
			stwcx

// RESERVATION cleared

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			.....
			.....
			lwarx

// Get RESERVATION again

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stwcx

//Note here: RESERVATION is valid, address is the same.
So the result is commited, no retry for task A

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.....
			stwcx

//RESERVATION is cleared, retry atomic op for task B

Please be noted that reservation is only identified by

reservation bit

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and address operated on.  So different lwarx's on the same

address,

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may be considered as the same reservation.

Is this your reason we cannot do atomic operation in user space?

How about the kernel space? You can image it.
The context switching as above also happen in kernel space,
Why we can do atomic operation in kernel space, not do in user

space?

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You are assuming the context switching cause the reservation broken.
but we can do atomic operation in kernel space.  The context
switching really is the execption of processor, If we can
clear the wrong RESERVATION before exception return, I think
we can solve this problem. We can dummy stwcx. before
exception return or the processor automaticly clear the
reservation in exception.

Are you missing these important things?

-DAve

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I got it. I noticed that all of execption return in kernel did stwcx.
to clear the wrong reserved bit. See the source code.
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        .globl  ret_from_except_full
ret_from_except_full:
        REST_NVGPRS(r1)
        /* fall through */
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        .globl  ret_from_except
ret_from_except:
           ......
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restore:
        lwz     r0,GPR0(r1)
        lwz     r2,GPR2(r1)
        REST_4GPRS(3, r1)
        REST_2GPRS(7, r1)
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        lwz     r10,_XER(r1)
        lwz     r11,_CTR(r1)
        mtspr   SPRN_XER,r10
        mtctr   r11
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        PPC405_ERR77(0,r1)
        stwcx.  r0,0,r1                 /* to clear the reservation */

Ya, you found the point.  There is no problem for me about this
question.

- Leo