On Tue, 2006-08-22 at 18:07 +0800, Zang Roy-r61911 wrote:

The patch adds new hardware information table for mpic. This 
enables mpic code to deal with mpic controller with 
hardware behavior difference.

+		TSI108_CPU_BASE,
+		TSI108_CPU_STRIDE,
+		TSI108_CPU_IPI_DISPATCH_0,
+		TSI108_CPU_IPI_DISPATCH_STRIDE,
+		TSI108_CPU_CURRENT_TASK_PRI,

This isn't actually enough to get SMP working on a Tsi109, as the Tsi109
mailbox and doorbell registers don't behave like standard MPIC IPIs.

So far I've experimented with a hack that uses the doorbell registers:
Doorbell 0 delivers IPI 0 to processor 0
Doorbell 1 delivers IPI 1 to processor 0
Doorbell 2 delivers IPI 0 to processor 1
Doorbell 3 delivers IPI 1 to processor 1

I don't support IPI 2 and IPI 3, though it would be possible to use the
mailbox registers in a similar scheme. This approach works, but I've not
worked out how to cleanly integrate this with the rest of the MPIC
driver, and won't have any time to do this in the near future.

-- 
Adrian Cox [off-list ref]