So, like, the other day Benjamin Herrenschmidt mumbled:
[A bunch of SMP issues.]
The above is wrong, it prevents using the same kernel image on another
platform.
Same comment above... #ifdef is bad. You are entering from 0x100 with
address translation not disabled ?
quoted
+ bl clear_bats
bl load_up_mmu
Why do you need to call clear_bats here ? load_up_mmu should load BATs.
If it doesn't handle the high BATs, then fix it :)
quoted
+#ifdef CONFIG_I8259_LEVEL_TRIGGER
+ outb(0xfa, 0x4d0); /* level triggered */
+ outb(0xde, 0x4d1);
+#endif
Another change that breaks multiplatform... Can you explain precisely
what you are trying to acheive here ? If necessary, we can add an
argument to i8259_init. Or you could do the above in your platform
code ... though I agree it would be a bit ugly :)
OK. I don't have direct answers in hand for some of
these questions and issues. I'll get with original
authors and see what we can do clean this up!
Thanks!
jdl
Jon Loeliger wrote:
So, like, the other day Benjamin Herrenschmidt mumbled:
quoted
[A bunch of SMP issues.]
The above is wrong, it prevents using the same kernel image on another
platform.
quoted
Same comment above... #ifdef is bad. You are entering from 0x100 with
address translation not disabled ?
quoted
quoted
+ bl clear_bats
bl load_up_mmu
Why do you need to call clear_bats here ? load_up_mmu should load BATs.
If it doesn't handle the high BATs, then fix it :)
I will fix this...
quoted
quoted
+#ifdef CONFIG_I8259_LEVEL_TRIGGER
+ outb(0xfa, 0x4d0); /* level triggered */
+ outb(0xde, 0x4d1);
+#endif
Another change that breaks multiplatform... Can you explain precisely
what you are trying to acheive here ? If necessary, we can add an
argument to i8259_init. Or you could do the above in your platform
code ... though I agree it would be a bit ugly :)
The above code is a must-have on our 8641D HPCN board to get PCI-Express
ULI1575 southbridge going. The 8259(which is residing inside the
southbridge) is collecting all PCI devices' interrupts( from both inside
the ULI1575 and at its external PCI slots) before it reports to MPIC.
PCI interrupts are level-triggered and shared thus we have to configure
8259 to be level-triggered on this particular board.
OK. I don't have direct answers in hand for some of
these questions and issues. I'll get with original
authors and see what we can do clean this up!
Thanks!
jdl
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On Fri, 2006-06-09 at 11:05, Jon Loeliger wrote:
quoted
quoted
+ bl clear_bats
bl load_up_mmu
Why do you need to call clear_bats here ? load_up_mmu should load BATs.
If it doesn't handle the high BATs, then fix it :)
Ben,
This line item has finally come around on the guitar!
And I have a question for you...
How come this additional clear_bats call isn't seen
as a generic fix? It is possible that the bootloader
has left some crufty (high) BATs hanging around.
Or are you suggesting just adding something like:
li r10, 0
mtspr SPRN_DBATxU,r10
mtspr SPRN_DBATxL,r10
for x in (4 .. 7) to the tail end of load_up_mmu as
the general fix?
Thanks,
jdl