Thread (17 messages) 17 messages, 8 authors, 2006-05-26

Re: [Cbe-oss-dev] Cell and new CPU feature bits

From: Segher Boessenkool <hidden>
Date: 2006-05-19 07:49:18

quoted
I'm assuming you mean the instructions described under "AltiVec  
Memory
Bandwidth Management" in secion 5.2 of the Altivec PEM -- dst, dstt,
dstst, dss and dssall?
They are nops on the Cell though.
And that is a compliant implementation.  I don't see a need
or real use for a feature bit here, esp. if we do get one for
the extended dcbt insns (which often are used as a replacement
for the data streaming insns).
They are also microcoded on the 970.
No, they are cracked, instead.  Much lower hit.  They are completion
serialized though, so the only insn in an issue group, etc.


Segher
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