Re: Linux Kernel Issue: MPC8540 Errata (CPU29)

Chiradeep,

I have the same issue with gcc3.4.3 and an e500 target.  You can give
gcc the -mno-string to inhibit generation of those load/store string
instructions.  I don't know if gcc can be configured such that its
default is not to generate those instructions.

Cheers,
Kylo

On 4/28/05, Chiradeep Vittal [off-list ref] wrote:

It turns out to be a compiler issue.
We're using gcc 3.4.3 with optimization level -Os. The following program =

will generate the illegal instruction with -Os but not with -O2

        int main (int argc, char** argv)
        {
          int seq[] =3D {0, 1, 2};
          return 0;
        }
The reason is that the compiler generates code with the stswi instruction=

 which is not supported by the e500. Here's our compiler configuration:

Configured with: /home/steve/perforce/sw/opt/crosstool/build/powerpc-8540=

-linux-gnu/gcc-3.4.3-glibc-2.3.2/gcc-3.4.3/configure --target=3Dpowerpc-854=
0-linux-gnu --host=3Di686-host_pc-linux-gnu --prefix=3D/home/steve/perforce=
/sw/opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2 --with-c=
pu=3D8540 --enable-cxx-flags=3D-mcpu=3D8540 --with-headers=3D/home/steve/pe=
rforce/sw/opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/po=
werpc-8540-linux-gnu/include --with-local-prefix=3D/home/steve/perforce/sw/=
opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540=
-linux-gnu --disable-nls --enable-threads=3Dposix --enable-symvers=3Dgnu --=
enable-__cxa_atexit --enable-languages=3Dc,c++ --enable-shared --enable-c99=
 --enable-long-long

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Any recommendations?
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Thanks
--
Chiradeep
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-----Original Message-----
From: Kumar Gala [mailto:kumar.gala@freescale.com]
Sent: Wednesday, April 27, 2005 11:37 AM
To: Chiradeep Vittal
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
=20
On Apr 27, 2005, at 12:46 PM, Chiradeep Vittal wrote:
=20

quoted

We're running Linux Kernel 2.4.26 on an 8540 ADS derivative. We're
 seeing an
"illegal instruction" (SIGILL) exception under some circumstances
(during a pthread_create call). We were wondering if this could be a
symptom of
CPU29 and if there is a patch available for CPU29.

"CPU29 L1 instruction cache gets multiple entries for same line after
 change
in MSR[IS] bit "

www.freescale.com/files/32bit/doc/errata/MPC8540CE.pdf

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The way the Linux kernel manages the MMU on e500 it doesn't actually
ever modify MSR[IS] or MSR[DS].  They are always zero so I dont believe
you are hitting this errata.
=20
Are you running with math emulation turned on?  Do you know what the
instruction is that causes the SIGILL?
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- kumar
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