On Fri, Mar 25, 2005 at 02:05:20PM -0600, Tolunay Orkun wrote:

This would not be a problem for level triggered interrupts if 
enable_irq() cleared the pending IRQ bit before re-enabling the 
interrupt system if that particular interrupt was level triggered.

If there is a valid request still pending (i.e. external IRQ line is 
still asserted at the appropriate level) this would not cause loss of 
interrupt but in case there is no requester (i.e. all interrupts are 
properly acknowledged), the spurious interrupt due to delayed processing 
would be avoided.

Hmm, I think I agree with you. Let me think a little more and I'll 
probably add this additional ACK to 4xx PIC code.

Only thing which bothers me is that such hack will be 4xx specific, as 
none of PIC handlers I looked at (in arch/ppc) do this. So, I'm not 
quite sure it worth adding at all. After all, the way you use 
enable_irq/disable_irq isn't quite standard anyway :).

--
Eugene